Pixel readout development for the PANDA experiment Vertex 2009 Richard Wheadon

1. Pixel readout development for the PANDA experiment Vertex 2009 Richard Wheadon

2. PANDA @ FAIR HESR = High Energy Storage Ring • High luminosity mode • Luminosity = 2x1032 cm-2s-1 • p/p~10-4 (stochastic cooling) • High resolution mode • p/p~10-5(el. cooling < 8 GeV/c) • Luminosity = 1031 cm-2s-1 • FAIR: Facility for Antiproton and Ion Research. • PANDA: Pbar ANnihilation at DArmstadt: Multipurpose experiment addressing: • charmonium spectroscopy • glueballs and hybrids • hadrons in nuclear matter • open charm production • g-ray spectroscopy of hypernuclei

3. The PANDA apparatus http://www-panda.gsi.de/

4. Micro-vertex requirements • Good spatial resolution in r-phi • Momentum measurement of • pions from D* decays • Good spatial resolution specially in z • Vertexing, D-tagging • Good time resolution • rms 6 ns (at 50 MHz clock) • with 2·107 ann/s • Triggerless readout • Energy loss measurement • dE/dx for PID • Low material budget • low momentum of particles • (from some hundreds of MeV/c) • (<1% X0 for each layer) • Radiation hardness (~4·1013 n 1MeV eq /cm2 ) • (half year data taking, 15 GeV/c antip-p) • Different radiation load

5. MVD layout Micro Vertex Detector 4 barrel layers Inner layers: hybrid pixels Outer layers: double sided strips 6 forward disks 4 disks: hybrid pixels 2 disks: mixed pixels and strips SPD : ~11.5 Mpixels, 0.115 m2 SSD : 70 kstrips, 0.5 m2

6. Service routing Upstream access only – all forward services pass through barrel

7. Power cable Data cable Controller chip Bias capacitor Supply capacitors Sensor ToPiX readout chips Multilayer bus structure Proposed disk layout Small forward disks, only free parameter is chip size Chip active Sensors Inner diameter 22 mm Outer diameter 75 mm Chip active 11.6 x 11.0 mm Alternate front and back Zero chip active overlap Horizontal zero gap Vertical gaps bridged with longer pixels Module concept (highly volatile) Piggy-back controllers serve 2/3 ToPiX Daisy-chain controllers where occupancy allows Aluminium bus and cables

8. Cooling Disk split in two halves along the mid-plane Material for heat dissipation: foam POCO-HTC Embedded cooling capillary between the two halves All elements glued with thermal glue Problem: large glueing area - tests have to be performed POCO HTC Density: 09 g/cm3 Total power: 90 W Coolant Temperature: 20°C Max. Reached Temperature Poco Foam: 23°C POCO HTC: 21.7°C PG: 23.3 °C

9. Specs for the pixel readout • Pixel cell specs: • Pixel size: 100 mm x 100 mm. • Noise level: < 200 e- rms. • Linear dynamic range: up to 100 fC. • Power consumption: < 20 mW. • Selectable input signal polarity. • Leakage insensitive up to 50 nA. • ASIC specs: • Self triggering • Active area: O(1cm2) • Data rate: O(0.8Gbit/sec.) • Radiation tolerance: LHC grade. • Simultaneous time stamping and charge measurement. • No existing chip could match simultaneously all the PANDA requirements. • Custom solution under investigation. • Technology: CMOS 0.13 mm. • Epitaxial silicon being considered for the sensor.

10. Ifb reset freeze read_cmd read_le read_te config_phase 12 7 12 Cint le_reg latch preamp comp enable te_reg control logic mask baseline restorer cfg_reg 5 12 DAC Pixel cell architecture Registers use SEU tolerant logic (based on the DICE cell)

11. Pixel-ID LE-REG Hit logic TE-REG CFG-REG Pixel-ID LE-REG Hit logic TE-REG CFG-REG Pixel-ID Dummy hit generator LE-REG Hit logic TE-REG dummy pixel detect dummy pixel detect 12-bit Gray code counter Write column control DP clear Empty 16 storage cells 16 storage cells Full EoC event generator Almost full DP present EoC create Read Readout control Data serializer Busy Final ASIC architecture • Time-stamp (Gray encoded) distributed to the pixels and stored into local registers (à la ATLAS). • Sixteen cells deep-FIFO at the end of each column. • 800 Mbit/sec per cm2 max data rate. • Power supply: 1.2 V.

12. ToPiX2 prototype • Test chip produced in a MPW • Size: 5 mm x 2 mm • Column length: 12.8 mm • Column folding => full bus length Analogue Digital • Full pixel cell • Simplified end-of-column logic • Two folded columns with 128 pixels • Two short column with 32 pixels • Sixteen pixels with wire bonding pad

13. Readout setup for prototype GPIB GPIB LabVIEW FPGA Two options A: Virtex ‘transparent’ level shifter NI-FPGA pattern generator + triggered memory 25 MHz or 10MHz clock B: Virtex chip controller NI-FPGA read/write Virtex FIFO’s 50MHz clock Tek AFG 3252 Pulse generator NI PCI-7831R Pulse out Ext trig Attenuator 3.3V DOut Virtex II FPGA Evaluation board TP in 1.2V DOut 19 bits 19 19 DIn 3 bits 3 3 ToPiX2 DIn 12 bits 12 12 6 2.5V 6ch DAC DOut 4 bits 4 4 AIn 6 ch

14. Reconstructed pulse shape Internal test pulse (different channels)

15. Linearity External test pulse - linearity at low values distorted due to capacitance of input bond and trace

16. Baselines From threshold scan S-curve Outliers are bonded channels DAC correction reduces spread sigma to level of channel noise Baseline variation small after irradiation up to 35Mrad

17. Gain From internal test pulse Column 3 pixels have different amplifier parameters Linear variation across 32-ch groups due to resistance of calibration line – will be corrected Gain variation negligible up to 35Mrad

18. Noise From threshold scan S-curve Outliers are bonded channels External DAC at limit of precision so spread is due to limit of S-curve precision Limited increase in noise up to 35Mrad, fully recovered after annealing

19. Tail slopes – TOT From internal test pulse Column 3 pixels have different amplifier parameters Variation is due to very low feedback current, spread is as expected from process Irradiation causes up to factor 2 change (leakage current adding to applied feedback current) Final design will include DACs for each column to allow correction

20. Calibration with Am source Standard p-type sensor 300 mm thick:

21. s [ ] Energy threshold SEU Test performed at INFN-LNL, SIRAD facility Work in progress, but indication is that DICE cell in 0.13mm technology does improve SEU resistance, but not as much as for previous technologies

22. ToPiX2 prototype satisfies requirements considering triple redundance instead of DICE for SEU protection next step to add end of column logic, fully-differential I/O However… used “LM” process variant (6 thin + 2 thick metal layers) HEP standardising on “DM” (3 thin + 2 thick + 3 RF) routing harder, but can be done (shared bus for column pairs) PANDA clock recently changed from 50MHz to 160MHz new columns, new receivers, new simulations… implications for data transmission architecture Development continues on all fronts sensors, structure, cooling, low mass Al bus and cables… Conclusions

23. Extra slides

24. Discriminator time walk

25. b) a) Time-walk after correction 24 Calibration points 5 Calibration points

26. b) a) Jitter contribution Leading edge jitter Total jitter

27. Across chip ToT variation DToT/ToT (%) Discharge current (A)