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A consideration on FEC Bit error Performance of concatenation of Viterbi decoder and RS code

A consideration on FEC Bit error Performance of concatenation of Viterbi decoder and RS code. Yasuo Harada Matsushita Electric Industrial Co. Ltd. Concatenated Error Correction Scheme.

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A consideration on FEC Bit error Performance of concatenation of Viterbi decoder and RS code

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  1. A consideration on FEC Bit error Performance of concatenation of Viterbi decoder and RS code Yasuo Harada Matsushita Electric Industrial Co. Ltd. Yasuo Harada, Matushita Electric

  2. Concatenated Error Correction Scheme • Concatenation FEC scheme used in Digital Broadcasting system such as in Satellite, Cable, terrestrial system for MPEG2 data • Robust error correction feature is obtained by concatenation of Viterbi and RS code • Viterbi decoder in 802.11a phy specification and FEC option provide this improvement in 802.11e Yasuo Harada, Matushita Electric

  3. Features of Viterbi decoder • Viterbi decoder with a high error correction capability • Viterbi decoder produces burst bit error when errors occur over its correction capability • Interleave is very effective with concatenation of RS code and Viterbi decoder Yasuo Harada, Matushita Electric

  4. Example of Bit error performance simulation condition .AWGN No PhaseNoise 16QAM R=3/4 Packet Size 1 Word = 255 Byte (RS(255,239)) 1 Payload = 4 Word (1020 Byte) Interleave： MATRIX 255Byte×4 Yasuo Harada, Matushita Electric

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