1 / 36

DOUBLE-GATE DEVICES AND ANALYSIS

DOUBLE-GATE DEVICES AND ANALYSIS. 2004. 6. 22 발표자 : 이주용 2004-21599. OUTLINE. DG-HEMT / VMT Introduction Material growth and device fabrication DC and microwave characteristics Conclusion. BUT : SHORT CHANNEL EFFECT LIMITATION. VERTICAL SCALING LIMITATION. DOUBLE GATE HEMT.

overton
Download Presentation

DOUBLE-GATE DEVICES AND ANALYSIS

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DOUBLE-GATE DEVICES AND ANALYSIS 2004. 6. 22 발표자 : 이주용 2004-21599

  2. OUTLINE DG-HEMT / VMT • Introduction • Material growth and device fabrication • DC and microwave characteristics • Conclusion

  3. BUT : SHORT CHANNEL EFFECT LIMITATION VERTICAL SCALING LIMITATION DOUBLE GATE HEMT IMPROVEMENT OF HEMT’s PERFORMANCE: • REDUCTION OF GATE LENGTH: • (state of the art: Ft=562GHz , Fmax=330GHz for Lg=25nm) PARTICULARLY FOR Fmax

  4. BUT : SHORT CHANNEL EFFECT LIMITATION VERTICAL SCALING LIMITATION INTRODUCTION IMPROVEMENT OF HEMT’s PERFORMANCE: • REDUCTION OF GATE LENGTH: • (state of the art: Ft=562GHz , Fmax=330GHz for Lg=25nm) PARTICULARLY FOR Fmax gate 2 drain source ALTERNATIVE: ACTIVE LAYER DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE gate 1 BCB host substrate

  5. source gate 2 drain ACTIVE LAYER gate 1 BCB host substrate (GaAs) DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE No buffer layer (reduction of output conductance: Gd)

  6. source gate 2 drain ACTIVE LAYER gate 1 BCB host substrate (GaAs) DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE No buffer layer (reduction of output conductance: Gd) Two gate (improvement of transconductance: Gm) (reduction of gate resistance: Rg) (higher intrinsic capacitances: Cgs, Cgd)

  7. source gate 2 drain ACTIVE LAYER gate 1 BCB host substrate (GaAs) DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE No buffer layer (reduction of output conductance: Gd) Two gate (improvement of transconductance: Gm) (reduction of gate resistance: Rg) (higher intrinsic capacitances: Cgs, Cgd) Higher 2DEG density in the channel (Reduction of the source and drain resistances: Rs, Rd)

  8. source gate 2 drain ACTIVE LAYER gate 1 BCB host substrate (GaAs) IMPROVEMENT OF THE MAXIMUM OSCILLATION FREQUENCY (Fmax) higher unloaded voltage gain (Gm/Gd) Lower parasitic resistances DOUBLE-GATE HEMT’s (DG-HEMT) ON TRANSFERRED SUBSTRATE No buffer layer (reduction of output conductance: Gd) Two gate (improvement of transconductance: Gm) (reduction of gate resistance: Rg) (higher intrinsic capacitances: Cgs, Cgd) Higher 2DEG density in the channel (Reduction of the source and drain resistances: Rs, Rd)

  9. MATERIAL GROWTH

  10. d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) MATERIAL GROWTH 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd cm cm =5.10 cap layer InAlAs InAlAs 120 Å 12 schottky ß ß InAlAs InAlAs 50 Å spacer 100 Å InGaAs channel InGaAs 100 Å spacer InAlAs InAlAs 50 Å ß ß InAlAs InAlAs 120 Å schottky 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd =5.10 cm cm Cap layer InAlAs InAlAs 100 Å etch etch - - stop layers InGaAs InGaAs 2000 Å InP substrate

  11. d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) MATERIAL GROWTH 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd cm cm =5.10 cap layer InAlAs InAlAs 120 Å 12 schottky ß ß InAlAs InAlAs 50 Å spacer 100 Å InGaAs channel InGaAs 100 Å spacer InAlAs InAlAs 50 Å ß ß InAlAs InAlAs 120 Å schottky 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd =5.10 cm cm Cap layer InAlAs InAlAs 100 Å etch etch - - stop layers InGaAs InGaAs 2000 Å InP substrate

  12. d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) InAlAs InAlAs 100 Å InGaAs InGaAs 2000 Å InP substrate MATERIAL GROWTH 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd cm cm =5.10 cap layer InAlAs InAlAs 120 Å 12 schottky ß ß InAlAs InAlAs 50 Å spacer ACTIVE LAYER 100 Å InGaAs channel InGaAs 100 Å spacer InAlAs InAlAs 50 Å ß ß InAlAs InAlAs 120 Å schottky 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd =5.10 cm cm Cap layer etch etch - - stop layers

  13. d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) InAlAs InAlAs 100 Å InGaAs InGaAs 2000 Å InP substrate MATERIAL GROWTH 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd cm cm =5.10 cap layer InAlAs InAlAs 12 120 Å schottky ß ß InAlAs InAlAs 50 Å spacer ACTIVE LAYER 100 Å InGaAs channel InGaAs 100 Å spacer InAlAs InAlAs 50 Å ß ß InAlAs InAlAs 120 Å schottky 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd =5.10 cm cm Cap layer InAlAs InAlAs 100 Å etch etch - - stop layers InGaAs InGaAs 2000 Å InP substrate

  14. d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) InAlAs InAlAs 100 Å InGaAs InGaAs 2000 Å InP substrate MATERIAL GROWTH 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd cm cm =5.10 cap layer InAlAs InAlAs 120 Å 12 1st HEMT schottky ß ß InAlAs InAlAs 50 Å spacer ACTIVE LAYER 100 Å InGaAs channel InGaAs 100 Å spacer InAlAs InAlAs 50 Å ß ß 2nd HEMT InAlAs InAlAs 120 Å schottky 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd =5.10 cm cm Cap layer InAlAs InAlAs 100 Å etch etch - - stop layers InGaAs InGaAs 2000 Å InP substrate

  15. d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) d d 12 12 - - 2 2 Si Si - - - - doped doped (5.10 (5.10 cm cm ) ) InAlAs InAlAs 100 Å InGaAs InGaAs 2000 Å R (active layer) = 130 Ω InP substrate MATERIAL GROWTH 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd cm cm =5.10 cap layer InAlAs InAlAs 120 Å 12 1st HEMT schottky ß ß InAlAs InAlAs 50 Å spacer ACTIVE LAYER 100 Å InGaAs channel InGaAs 100 Å spacer InAlAs InAlAs 50 Å ß ß 2nd HEMT InAlAs InAlAs 120 Å schottky 18 18 - - 3 3 InGaAs InGaAs 100 Å Nd Nd =5.10 cm cm Cap layer InAlAs InAlAs 100 Å etch etch - - stop layers InGaAs InGaAs 2000 Å InP substrate

  16. DEVICE FABRICATION PROCESS

  17. CLASSIC HEMT PROCESS (1/4) • Mesa isolation. • Ni/Ge/Au/Ni/Au Ohmic contact. • Bonding pads. (Ti/Au/Ti) • First T-gate process: selective recess (Succinic Acid) Ohmic Contact Bonding Pad gate 1 Active Layer InAlAs etch-stop layer InGaAs etch-stop layer InP Substrate

  18. BONDING PROCESS (2/4) InP Substrate • BCB depositing on both active substrate and on GaAs host substrate. • Bonding. InGaAs etch-stop layer InAlAs etch-stop layer Active Layer gate 1 BCB GaAs host Substrate

  19. ETCHING PROCESS (3/4) • Etching InP Substrate by hydrochloric solution. • Etching InGaAs etch-stop layer by Succinic Acid solution. • Etching InAlAs etch-stop layer by H3PO4/H2O2/H2O solution. Active Layer gate 1 BCB GaAs host Substrate

  20. SECOND GATE PROCESS (4/4) Bonding Pad Ohmic Contact gate 2 • Second T-gate process: selective recess (Succinic Acid) Active Layer gate 1 BCB GaAs host Substrate

  21. gate 2 Ohmic contact Active layer gate 1 SEM photograph of a double-gate HEMT Bonding Pad gate 2 Active Layer gate 1 BCB Ohmic Contact GaAs host Substrate

  22. DC AND MICROWAVE CHARACTERISTICS

  23. Idmax = 500 mA/mm VP = -0.2 V Gmext = 2650 mS/mm I(V) CHARACTERISTICS W =2x50µm Lg1 = 0.1µm Lg2 = 0.28µm Vgmax = 0.2V Vgstep = -0.05V VGATE 1 =VGATE 2 • No Kink Effect • Good Pinch-Off

  24. MICROWAVE CHARACTERISTICS W =2x50µm Lg1 = 0.1µm Lg2 = 0.28µm Vds = 0.7 V Vgs = 0.1 V

  25. Gm Gm = 87 = 8 Gd Gd INTRINSIC PARAMETERS GmINT GdINT DG-HEMT Gm = 3140 mS/mm Gd = 36 mS/mm HEMT Gm = 1650 mS/mm Gd = 194 mS/mm

  26. VELOCITY MODULATION TRANSISTOR

  27. Vgt s D Vgb INTRODUCTION VMT?? • Two channels with differing velocities • Drain current =>controlled by modulating carrier velocity in source-drain channel Fast top channel Slow bottom channel Two channel gate Two gates work in tandem => can maintain total channel population

  28. BUT : limited by source-drain transit time top and back gate capacitance should be equal CHARACTERISTICS Two channel of differing velocity Opportunity for higher speed than C-HEMT HEMT-like Noise Useful in ADCs and AMP Rapid switching time

  29. 0<t<tswitch Id=HIGH Vgt ”HIGH” Vgt ”LOW” Vgt ”LOW” s s s D D D Vgb ”LOW” Vgb ”HIGH” Vgb ”HIGH” t=0 Id=HIGH t=0 Id=LOW

  30. + + + ----- ----- VMT CONDUCTION BAND + + + ----- ----- AlGaAs GaAs AlGaAs AlGaAs GaAs AlGaAs ( Biased to off ) ( Biased to on )

  31. n-GaAs 50 Å n-AlGaAs 600 Å 200 Å i-AlGaAs i-GaAs 450 Å i-AlGaAs (graded) 40 Å i-GaAs 300 Å n-GaAs 140 Å 800 Å i-AlGaAs p-GaAs 2um Semi insulating GaAs substrate Material growth and device fabrication Top side processing only 600℃ 2 DEG Channel isolation and preventing defect Separate high and low channel Low mobility channel (Donor ion and As defect) 550℃ P+ back gate 600℃

  32. EXPERIMENT (1) Topand bottom channel concentration VMT top channel concentration Top Lg=40nm HEMT channel concentration Sheet carrier concentration

  33. EXPERIMENT (2) I-V characteristic on state Vgt=-0.85V Vgb=-1.06V off state Vgt=-2.20V Vgb=0V

  34. EXPERIMENT (3) Ft=15GHz Fmax=100~600GHz Cbottom=KcCtop

  35. CONCLUSION • 0.1µm/0.28µm InAlAs/InGaAs DG-HEMTs: • highextrinsic transconductance = 2650mS/mm • fT = 110GHz fMAX = 200GHz • high unloaded voltage gain (gm/gd = 87) • Velocity Modulation Transistor: • easy fabrication process • low fTbutfMAX = 100~600GHz • faster switching time

  36. REFERENCE [1] Y. YAMASHITA et al. "Pseudomorphic In0.52Al0.48As/In0.7Ga0.3As HEMTs with an ultrahigh ft of 562GHz" IEEE Electron Device Letters, vol.23, n°10, October 2002, pp.573-575. [2] A. ENDOH et al. "Fabrication technology and device performance of sub-50nm gate InP based HEMTs", Proceeding of IPRM2001, pp.448-451. [3] G.K. CELLER et al. "Frontiers of silicon-on-insulator", Journal of Applied Physics, vol.93, n°9, pp.4955-4978, 2003. [4] M.J.W. RODWELL et al, "Submicron Scaling of HBTs", IEEE trans. on elect.devices,vol.48,n°11,pp.2606-2624,2001. [5] S. B0LLAERT et al, "0.12 μm gate length In0.52Al0.48As/In0.53Ga0.47As HEMTs on transferred substrate", Electron Device Letters, vol.23, n°2, pp.73-75, 2002. [6]Fabrication and operation of a velocity modulation transistor Webb, K.J.; Cohen, E.B.; Melloch, M.R.; Electron Devices, IEEE Transactions on , Volume: 48 , Issue: 12 , Dec. 2001 [7]Analysis of microwave characteristics of a double-channel FET employing the velocity-modulation transistor concept Maezawa, K.; Mizutani, T.;Electron Devices, IEEE Transactions on , Volume: 39 , Issue: 11 , Nov 1992 [8]H.Sakaki," velocity-modulation transistor(VMT)-A new field effect transistor concept." Japan.J Appl.Phys vol.21 [9]K.Maezawa, T.Mizutani, and S.Yamada " GaAs/AlAs double-channel structure for velocity modulation transistor."to el published in Japan 1992

More Related