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Strategy for unified data link

Strategy for unified data link. Zhen-An LIU Institute of High Energy Physics. New Ideas on Belle II DAQ. Consideration Base HS data transmission Optical link Unified Readout Unified Data link Also trigger? Also timing? My talk on PMC/COPPER link. Trigger path suggestion to Iwasaki-san.

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Strategy for unified data link

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  1. Strategy for unified data link Zhen-An LIU Institute of High Energy Physics

  2. New Ideas on Belle II DAQ • Consideration Base • HS data transmission • Optical link • Unified Readout • Unified Data link • Also trigger? • Also timing? • My talk on PMC/COPPER link

  3. Trigger path suggestion to Iwasaki-san • If HS data link used • RocketIO (SEDES) • Synchronization needed (per channel) • Channel Alignment needed (per system) • Pipelined processing • Trigger latency should reserve big enough • 5 us maybe enough but conservative • 7 us in BESIII • Trigger distribution • More time needed

  4. Scheme1 for Data link (to Copper) • Based on discussions two schemes in consideration • Scheme 1 • Detector specific readout( Gary’s board or other?) • 16 ch/optical line • Data preprocessing • Partial packaging • Data frame/protocol • Length/ch/event? • Trigger L1 driven • Data merger • Further packaging • Necessary to save COPPER boards • Output to COPPER PMC • Data frame2 • PMC • Data mover to CPU on COPPER

  5. Merger test module To COPPER PMC Power Supply LT1764EQ-DD 1.5V,2.5V,3.3V,5V 1.6~2.5V Adjustable VME BUS Optical Fiber0 Download circuit HFBR5921L 0 Control Signals Via USER pins Optical Fiber 1 HFBR5921L 1 XC2VP40 FF1152-6 1.6 GBps /ch 5V/3.3V Bus Switch IDT QS316211 From Unified Readout Optical Fiber 8 D(0:31) SN74 ALVTH 162245 HFBR5921L 8 D(0:31) Optical Fiber 9 HFBR5921L 9 CDCF 5801 80MHz SN74ALVTH162244 MC100 EP16FD Clock (40MHz) 95 Con LED Display 16 Test Pin Test output 34 Pin LVDS SN75LVDS387 LVTTL-LVDS 16 Test Pin 95 Con 16 Test Pin Reserved 34 Pin LVDS SN75LVDS387 LVTTL-LVDS 16 Test Pin 16*12 Test Pins

  6. To be decided with Scheme 1 • Clock for HS transmission • System clock • How many input ch / board? • Data rate • Data size • VirtexII Pro / VirtexV ? • Synch/Asych? • Synchronized data transmission. • Data frame

  7. Status • Hardware available • Data source • Merger board • Test system available • Protocol • Need FRST, Tsync signals from timing sys. • Need more discussion with timing/readout/COPPER people • PMC to be designed

  8. Scheme2 for Data link • In scheme 1: • Optical transceiver inside detector( say CDC) • Question: • Reliability not so good in BESIII • Radiation? Experiment did before design • ESD effect? Experiments under taken • Unclear yet! • Stop machine for replacement? • Open the Detector for replacement? • Possible solution • Optical transceiver outside detector • Merger before HS data link

  9. Scheme2 for Data link • Scheme 2 • Merger near detector • Electrical to FEE • Optical to PMC/COPPER • Easy maintenance • SFP transceiver

  10. More discussion scheduled • A discussion is scheduled tomorrow • Idea from detector and FEE welcome

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