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Silicon South West, Testing Times The Economics of Verification Mike Bartley, TVS

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Silicon South West, Testing Times The Economics of Verification Mike Bartley, TVS

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    2. How can verification deliver value? What is verification? The economics of verification 100% verification is IMPOSSIBLE How to do verification successfully

    3. The various RTL verification techniques

    4. Verification consumes the greatest design time Need to explain the graph There are a number of surveys into the distribution of effort in Silicon development – they ALL point to: Verification takes most effort The % of effort and absolute cost is INCREASING Software development is now the second largest portionNeed to explain the graph There are a number of surveys into the distribution of effort in Silicon development – they ALL point to: Verification takes most effort The % of effort and absolute cost is INCREASING Software development is now the second largest portion

    5. Poor verification costs money in re-spins “Half of all chip developments require a re-spin, three quarters due to functional bugs”, The 2004/2002 IC/ASIC Functional Verification Study by Collett International Research Consider a tape-out at risk – what would you want to know? What are the chances of a killer bug that renders it useless? Will we have the major features working? Your verification planning should prioritise testing to make such decisions possible Consider a tape-out at risk – what would you want to know? What are the chances of a killer bug that renders it useless? Will we have the major features working? Your verification planning should prioritise testing to make such decisions possible

    6. Economic impact of Verification Inefficient verification It is your biggest design task! Delays to market Ineffective verification Your biggest cause for re-spins (and recalls) Economics of early release Better, faster verification Tape-out early with measurable risk Consider a tape-out at risk – what would you want to know? What are the chances of a killer bug that renders it useless? Will we have the major features working? Your verification planning should prioritise testing to make such decisions possible Consider a tape-out at risk – what would you want to know? What are the chances of a killer bug that renders it useless? Will we have the major features working? Your verification planning should prioritise testing to make such decisions possible

    7. Consider an adder 16 bits ? 8.5 billion tests > 2500 years @ 1 test/second 2x x 2x x 2y possible input conditions per transition Impossible to prove the absence of bugs Why is 100% verification impossible?

    8. What we want from verification Demonstrate absence of bugs Build confidence to ship the product Defining measurable exit signoff criteria Demonstrate correctness of prioritised features Mitigate risk And stop when cost of further verification outweighs the advantages of increased confidence

    9. Beginning verification earlier brings benefits

    10. Team independence in verification How hard does somebody try to break their own design? Verification engineers require different skills and attitudes Reconvergent paths (Bergeron 2000)

    11. Good engineering principles delivers benefits Processes Stable, clear specifications under change control Configuration and defect management Maximise re-use Well defined signoff targets People Verification engineers require different skill sets Independence Appropriate tools and methodologies Note that at Dialog The signoff targets are not consistent across ALL projects The signoff targets are NOT always met There is not always a signoff meeting to understand the status on the targets (and thus the risk)Note that at Dialog The signoff targets are not consistent across ALL projects The signoff targets are NOT always met There is not always a signoff meeting to understand the status on the targets (and thus the risk)

    12. And what about software! 20% hardware, 80% software? Is the Toyota Prius recall the software equivalent of the Intel FPU bug?

    13. Summary About TVS About DVClub “Design IP – help or hindrance to verification”, April 26th What is verification Why you should care Managing it mike@tandvsolns.co.uk Questions?

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