1 / 23

OIF 10Gbps Electrical Interfaces

OIF 10Gbps Electrical Interfaces. Tom Palkert AMCC Supercomm 2003. OIF 10 Gbps Common Electrical Interfaces (CEI). CEI-SR = Short Reach (0-200mm + one connector) Intended for chip to optical module or chip to chip interfaces 5-6Gbps 10-11 Gbps CEI-LR = Long Reach (0-1m + two connectors)

rolanda
Download Presentation

OIF 10Gbps Electrical Interfaces

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. OIF 10Gbps Electrical Interfaces Tom Palkert AMCC Supercomm 2003

  2. OIF 10 Gbps Common Electrical Interfaces (CEI) • CEI-SR = Short Reach (0-200mm + one connector) • Intended for chip to optical module or chip to chip interfaces • 5-6Gbps • 10-11 Gbps • CEI-LR = Long Reach (0-1m + two connectors) • Intended for chip to chip interface over a backplane • 5-6Gbps • 10-11 Gbps

  3. Future OIF interfaces that could leverage the CEI specifications • SFI = SERDES to Framer • SPI = System Packet Interface • TFI = TDM Fabric Interface

  4. TransmitLink Layer Device Optical Interface Receive Link Layer Device SERDES Device and Optics T F I CEI Common Electrical Interface System Packet Interface (SPI) SERDES Framer Interface (SFI) SERDES Framer Interface (SFI) CEI CEI CEI PHY Device FEC Data Status Data Data Data OR Status Data Data Data Data TDM Fabric to Framer Interface (TFI)

  5. CEI Common Electrical Interface SERDES Framer Interface (SFI) SERDES Framer Interface (SFI) System Packet Interface (SPI) Transmit Interface (SPI) PHY Device FEC Device SERDES Device and Optics TransmitLink Layer Device Data Data Data Status Receive Link Layer Device Data Data Data Status Receive Interface (SPI) Provide well defined voltage levels and timing budgets

  6. CEI Common Electrical Interface S y s t e m t o O p t i c s TXREFCK TXREFCK TXREFCK TXDATA [n:0] TXDATA [n:0] Framer FEC Processor Serdes TXDSC TXDSC RXDATA [n:0] RXDATA [n:0] RXREFCK RXREFCK O p t i c s t o S y s t e m Deskew required to align data channels

  7. CEI-SR Common Electrical Interface SERDES Framer Interface (SFI) SERDES Framer Interface (SFI) System Packet Interface (SPI) Transmit Interface (SPI) PHY Device FEC Device SERDES Device and Optics TransmitLink Layer Device Data Data Data Status 8“ 8“ 8" Receive Link Layer Device Data Data Data Status Receive Interface (SPI) Capable of driving at least 8 inches/200mm of FR4 with 1 connector

  8. CEI-LR Common Electrical Interface SERDES Framer Interface (SFI) SERDES Framer Interface (SFI) TDM Fabric Interface (TFI) PHY Device FEC Device SERDES Device and Optics T F I Data Data Data 1m 8" 8" Data Data Data Status Capable of driving at least 1m of backplane with 1 or 2 connectors

  9. CEI Common Electrical Interface Ideal 0-crossing point Ideal 1-crossing point Sampling point True Complement Jitter : Phase variations in a signal (clock or data). Total Jitter is composed of both deterministic and random content.

  10. OIF Common Electrical Interface for Short Reach applications

  11. OIF-SFI-4 phase 1 Electrical Interface REFCLK REFCLK REFCLK TXDATA [15:0] TXDATA [15:0] Framer FEC Processor C D Serdes C D TXCLK TXCLK TXCLKSRC TXCLKSRC B A B A RXDATA [15:0] RXDATA [15:0] RXCLK RXCLK A B B A S y s t e m t o O p t i c s O p t i c s t o S y s t e m System Reference Model, OIF-SFI-4 phase 1 implementation agreement 16 LVDS data lanes and clocks for a bi-directional, 10 Gb/s interface

  12. OIF-SFI-4 phase 1  OIF-SFI-4 phase 2 Phase 2 Phase 1 Phase 2 Phase 1 REFCLK REFCLK REFCLK TXDATA [3:0] TXDATA [15:0] TXDATA [15:0] TXDATA [3:0] Framer FEC Processor C D Serdes C D C D C D TXCLK TXCLK TXCLKSRC TXCLKSRC B A B A RXDATA [3:0] RXDATA [3:0] RXDATA [15:0] RXDATA [15:0] RXCLK RXCLK B A B A A B B A Phase 1 Phase 2 Phase 1 Phase 2 S y s t e m t o O p t i c s O p t i c s t o S y s t e m

  13. Possible OIF-SFI-4 phase 3 Interface S y s t e m t o O p t i c s REFCLK REFCLK REFCLK Framer FEC Processor Serdes TXDATA [1] TXDATA [1] 8“/200mm 8“/200mm RXDATA [1] RXDATA [1] O p t i c s t o S y s t e m Capable of driving at least 8”/200mm of FR4 interconnect with one connector

  14. Possible OIF-SFI-4 phase 3 Interface S y s t e m t o O p t i c s REFCK REFCK REFCK Framer FEC Processor Serdes TXDATA [1] TXDATA [1] OC-192 10GbE FEC RXDATA [1] RXDATA [1] O p t i c s t o S y s t e m Support for an aggregate, 9.9-11+ Gb/s, bi-directional throughput such as 10 GbE, SONET OC-192 and other systems, including FEC overhead.

  15. Possible SFI-5 phase 2 Interface(OC-768 SERDES to Framer) using CEI-SR

  16. Possible SFI-5 phase 2 OC-768 SERDES to Framer Interface using CEI-SR S y s t e m t o O p t i c s TXREFCK TXREFCK TXREFCK TXDATA [3:0] TXDATA [3:0] Framer FEC Processor Serdes SONET OC-768 SDH STM-256 OTN OTU-3 RXDATA [3:0] RXDATA [3:0] RXREFCK RXREFCK O p t i c s t o S y s t e m

  17. Possible SFI-5 phase 2 OC-768 SERDES to Framer Interface using CEI-SR S y s t e m t o O p t i c s TXREFCK TXREFCK TXREFCK Framer FEC Processor Serdes TXDATA [3:0] TXDATA [3:0] 8“/200mm 8“/200mm RXDATA [3:0] RXDATA [3:0] RXREFCK RXREFCK O p t i c s t o S y s t e m Supports 8”/200mm of FR4 interconnect with one connector

  18. SFI-5 OC-768 SERDES to Framer Interface S y s t e m t o O p t i c s TXREFCK TXREFCK TXREFCK Framer FEC Processor Serdes TXDATA [3:0] TXDATA [15:0] EFEC GFEC RXDATA [3:0] RXDATA [3:0] RXREFCK RXREFCK O p t i c s t o S y s t e m Supports Forward Error Correction (FEC).

  19. Possible SFI-5 phase 2 OC-768 SERDES to Framer Interface using CEI-SR S y s t e m t o O p t i c s TXREFCK TXREFCK TXREFCK TXDATA [3:0] Framer FEC Processor Serdes TXDATA [3:0] DATA [3:0] 9.9-11+Gbps DATA [3:0] 9.9-11+ Gbps RXDATA [3:0] RXDATA [3:0] RXREFCK RXREFCK O p t i c s t o S y s t e m 4-bit wide data bus

  20. TFI TDM Fabric to Framer Interface

  21. Reference Diagram SONET Framer SONET Signals SONET/SDH OC 3/12/48/192/768 SONET Framer FEC Processor G.709 OTN OTM 1/2/3 TDM Switch Fabric Non-SONET Signals SONET Framer 10GE LAN PH Processor 10GE LAN PHY TFI

  22. TFI Requirements SONET/SDH OC 3/12/48/192/768 SONET Framer SONET Signals G.709 OTN OTM 1/2/3 SONET Framer FEC Processor TDM Switch Fabric Non-SONET Signals 10GE LAN PHY SONET Framer 10GE LAN PH Processor TFI

  23. Possible TFI-5 phase 2 Interface based on CEI (cont.) Support lane bandwidths of 9.9-11+ Gb/s SONET Framer SONET Signals SONET/SDH OC 3/12/48/192/768 SONET Framer FEC Processor G.709 OTN OTM 1/2/3 TDM Switch Fabric Non-SONET Signals SONET Framer 10GE LAN PH Processor 10GE LAN PHY TFI - 5 Supports de-skew between lanes Capable of driving at least 1m of Printed Circuit Board with 2 connectors for intra-shelf environments

More Related