The FVTX detector in PHENIX

1. The FVTX detector in PHENIX Forward Silicon Vertex Detector, one of a number of detector upgrades Hubert van Hecke, Los Alamos National Laboratory for the PHENIX collaboration Vtx (Mannel) Fvtx (HvH) RPC (Wei) TOF (Belmont) RPC gas (Wood) RPC (Kim) RPC (Meredith) Computing (Love)

2. FVTX team R. K. Choudhury, P. Shukla, D. Dutta, A. K. Mohanty, Bhabha Atomic Research Centre, India; R. Pak, K.A. Drees, Brookhaven National Laboratory; H. Pereira, Saclay, France; M. Finger, M. Finger, Charles University, Prague, Czech Republic; J. Klaus, Czech Technical University, Prague, Czech Republic; P. Mikes, J. Popule, L. Tomasek, M. Tomasek, V. Vrba; Institute of Physics, Academy of Sciences, Prague, Czech Republic; B. Cole, E. Mannel, D. Winter, W. Zajc, Columbia University; J.C. Hill, J.G. Lajoie, C.A. Ogilvie, A. Lebedev, H. Pei, G. Skank,A. Semenov, G. Sleege, F. Wei, Iowa State University; Naohito Saito, KEK, Japan; T. Murakami, K. Tanida, Kyoto University, Japan; J.G. Boissevain, M.L. Brooks, S. Butsyk, G. Grim, H.W. van Hecke, J. Kapustinsky, A. Klein, G.J. Kunde, D.M. Lee, M.J. Leitch, H. Liu, M.X. Liu, P.L. McGaughey, A.K. Purwar, W.E. Sondheim, Los Alamos National Laboratory; Hisham Albataineh, G. Kyle, V. Papavassiliou, S. Pate, X.R. Wang, New Mexico State University;T. Alho, M. Bondila, R. Diaz, D. J. Kim, J. Rak, University of Jyvaskyla, Finland;B. Bassalleck, D.E. Fields, M. Hoeferkamp, M. Malik, K. Spendier, J. Berndt, University of New Mexico, Albuquerque; J.H. Kang, Y. Kweon, Yonsei University, Korea

3. Goals of the FVTX • Use heavy quarks (c,b) to study • properties of the QGP • q, g contributions to p spin • Drell-Yan • Signal channel: • b->B-> • c->D->  • J/, ’->   m+ m- B,D have finite lifetimes, so they can be identified with a vertex tracker

4. Separate signal from backgrounds The problem: backgrounds (->m and K-> m) overwhelm the signal Solution: D, B mesons travel ~1mm (with boost) before semileptonic decay to muons Mean ,K decay distance is much larger By measuring the DCA to the primary vertex, we can separate D, B decays from prompt muons and from long-lived decays from , K

5. Detector Specifications • Need sufficient DCA resolution (~100um) • Need occupancy low enough to find tracks in central AuAu events (<few %) • Need enough hits to reconstruct a track (>=3 hits) • Need to match tracks with Muon System:  = 1.2 - 2.4

6. HDI Sensor Model the detector 11.2mm strip 12.5 cm 1664 strips 13 chips 75-um strips Geant-3-based simulations 3.750 2.8mm strip

7. Other materials Materials that affect us: - barrel silicon layers (4) - support and cooling structures - cabling and connectors - beam pipe - electronics board

8. DCA resolutions Since the barrel pixels are // to the beampipe (orthogonal to the FVTX mini-strips, using them greatly improves phi resolution

9. Occupancy Max track density in central Au+Au ~7/cm2 /cm2 -> choose 75 m strips Max. strip occupancy ~ 2.8%

10. Open charm, bottom signal Using DCA cuts, plus  and isolation cuts, we can now improve the signal/background for D,B->

11. Improved resolution + background reduction Simulated RHIC-II p+p run - better background . rejection - better mass resolution - separate ’ Without FVTX With FVTX

12. Mechanical design and prototypes Main unit: ‘wedge’ Heat flow studies Carbon backing Kapton HDI Silicon Readout chips Min Tº = 15ºC Max Tº = 20.3ºC Mechanical distortion studies Silicon sensor prototype from ON Semiconductor, CZ, under test at UNM Max deflection 10.4μm

13. Wedge -> Disk -> Cage assembly Support cage Mechanical design ~80% done Wedges front and back 40 cm Honeycomb support panel Cooling out 16.1°C Thermally conducting silicone Cooling inlet 15°C

14. Readout chain FVTX readout chips ROC read-out card nearby FEM front-end module outside experimental hall

15. 1) Readout chip (FPHX) Readout chip being designed at FNAL Derived from FPIX family of chips (BTeV), with (small) modifications ‘Pushes’ data to ROC - total bandwidth up to ~3.5 Tbps Low power: 100 W/channel, 50W total / 4 disks 2x13 chips per wedge, 128 channels / chip Total # channels: ~1.0M

16. 8-chip HDI USB Interface Actel Starter Board 2) ROC - readout card • One ROC combines data from 26 FPHX chips, send zero-supressed data to FEM over optical link • Download masks and thresholds to FPHX • Send clocks • Control calibration board • Implemented in rad-hard Actel FPGA prototype

17. 3) FEM: front-end-module • FEM buffers data by beam crossing, 64 clocks deep • Deliver event upon LVL-1 trigger to Phenix DAQ • Send clocks down to IR • Implemented in Xilinx FPGA

18. Test with prototype readout chip and ROC Calibration using FPIX chips and readout cardprototype: Threshold / noise ~ 18:1

19. Status and outlook Software: - Simulations and analysis - in hand Hardware: - Silicon detector prototypes undergoing tests - FPHX chip being layed out - HDI (Kapton interconnects) being layed out - Readout electronics chain prototyped and running - Mechanical design ~80% done - Construction start in FY08 - Installation in Phenix in summer 2011

20. backups

21. External mount

22. skip Acceptance Since the event vertex spans ~+-10 cm in z, we can use the barrel hits for some events.

23. skip Can we match muon arm tracks with a FVTX track? Use the chi2 of the Kalman track fitter : 3 GeV muon: 75% correct match 9 GeV muons; 93% correct match