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PHENIX Upgrade: Stripixel VTX detector

This mini workshop discusses the physics goals and components of the Stripixel VTX detector in the PHENIX Upgrade.

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PHENIX Upgrade: Stripixel VTX detector

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  1. PHENIX Upgrade:Stripixel VTX detector PHENIX Upgrade Mini Workshop January 21st 2011, RIKEN Akitomo Enokizono (Oak Ridge National Laboratory)

  2. Outline • Physics Goals • Overview of Strip VTX detector • Stripixel components • Stripixel sensor, ROC • RCC, PariPoser • LDTB, bus cable • DIB/CIB • Summary A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  3. Measurement improvements with VTX • Properties of QGP • Clear separation of heavy flavor (c, b) for RAA, v2 measurements. • Direct measurement of open beauty B -> J/ + X. • Wide coverage (central to forward w/ FVTX) to understand QGP and cold nuclear matter effects, and to observe broad x-range. • Reduction of backgrounds • Gluon spin structure • Gluon polarization (G/G) with charm/beauty separation • x dependence of G/G with -jet correlation • Others • More acceptance for jet reconstruction • Soft physics with low-pT PID • Drell-Yan measurements accessible A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  4. Distance to the Closest Approach • Use simulation and knowledge of D, B kinematics to obtain dN/dxDCA for decay electrons • Measure yield of electrons integrated above a DCA cut as a function of the DCA cut • Fit the yield vs. DCA to the known shapes for B, D and background e+, e-. A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  5. Heavy flavor physics programs Clear separation of heavy flavor (c, b) productions • PHENIX has observed strong suppression (RAA<1) and elliptic flow (v2) for electrons from heavy flavors in Run4, but ce and be are not separated. • With VTX, we can observe RAA for cand be separately. Au+Au 200 GeV RUN4 Au+Au 200 GeV PRL98,172301 PRL98,172301 (2007) Run7 Preliminary Rapp & van Hees, PRC 71, 034907 (2005) Expected w/ VTX (0.4/nb ~3 weeks in Rrun11) A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  6. GRSV_std GRSV_std Dg = -g Dg = -g Dg = g Dg = g Spin physics program • VTX/FVTX will be able to measure gluon polarization (via ALL) for different channels (gg, gq0,,cc-bar, bb-bar, +jet +X) that cover different kinematic regions in x and Q2. Double Spin Asymmetry L = 300 pb -1 P = 0.7 200mm < DCA A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  7. PHENIX central VTX detector overview VTX support structure VTX space frame Inner two layers: Pixel detector L1: R=2.5cm z=10cm L2: R=5.0cm z=10cm Outer two layers: Stripixel detector L3: R=10.4-12.8cm z=16cm L4: R=15.4-17.6cm z=19cm West Half East Half “Big Wheel” regions in Gas enclosure, where SPIRO, LDTB mounted Kinematic mounts to align the two halves ||<1.2, ~2 (145/each arm) A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  8. PHENIX strip-VTX detector overview (1) Sensor module (ROC + 12 SVX4 chip + sensor) Carbon composite Stripixel Stave (skins + core + Al cooling tube) Bus cable Readout Control Chip (RCC) Large Data Transfer board (LDTB) Serial Control (USB) VME BCLK/Controls (Glink card) DCM CIB DIB x 20 A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  9. PHENIX strip-VTX detector overview (2) 3rd layer: 8x2 full stripixel ladders = 80 sensor modules (5/ladder) 4th layer: 12x2 full stripixel ladders = 144 sensor modules (6/ladder) Layer 3 half ladder Layer 4 half ladder Total: 40 ladders (stave, bus, LDTB) 224 ROCs (sensors), RCCs 344064 channels A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  10. Stripixel Silicon sensor R. Nouicer et al. JINST 4:P04011,2009) • Stripixel sensor • 1 side, 2 direction read-out • Size : 3.5 x 6.4 cm2, thickness 625m • 80 m x 1000 m pixel size • 768 X + 768 U strips = 1536 channels • DC coupled • Operate at 200V bias for the final setup. • Wafer is produced and inspected at HPK A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  11. Readout card (ROC) • SVX4: • 8-bit ADC, 3mW / channel, 128 channel / chip • SVX4 operation is controlled through a 21-line data bus. • Programmable analog pipeline (42 cells for data, 4 cells for trigger buffer, 1 for amplifier pedestal) • Real time pedestal correction. • ROC: • 12 svx4 chips / sensors • Serial control loop for three svx4 chips (hybrid) • Passive components on back • ½ oz Cu grounding layer • Readout from J1/J2 connectors A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  12. Sensor modules, ladders assembly Wire-bonding, encapsulation of the ROC-SVX4-Sensor and precisionplacement of the silicon sensor (FNAL) Placing modules on stave, modules alignment, ladder survey (BNL) A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  13. SVX4 digital activity test • Two level1 signals are issued with some delay to check how much svx4 digital activity affect the later event. • The svx4 digital activity has been mitigated by improving the grounding. ROC3 Actual worst digital activities shift the pedestal by ~15-20ADC/channel. ppROC Events with all adc channel saturated) appears 138 clocks period due to the pri-amp reset and we can avoid such events in actual DAQ. Actual worst digital activities shifts the pedestal by ~5-6ADC/channel. A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  14. Performance with test beam • Sensor performance has been tested with FNAL 120GeV proton beam in 2008. • X-stripixel 0.42 x 80 (mm) = 33.6 (mm) • U-stripixel 0.44 x 80 (mm) = 35.2 (mm) A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  15. Readout Control Chip (RCC) • FPGA: AX125-CS180 • ACTEL Antifuse 0.15um Technology • One time programmable • RCC logic is completely triplicated. • Low single event upset rate. • Functions: • Select hybrids to operate. • Pass clocks, commands, lvl1 singals • All 6(5) RCCs are operated in parallel. • The first chip on each RCC is presented simultaneously to the LDTB. • If a hybrid is disabled the RCC pads its data so that the format remains unchanged. • On Hughes rigid flex circuit boards • Connections • J1/J2 wings to ROC J1/J2, and J8 to bus cable. • PariPoser material and PEEK screw are used. PEEK A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  16. PariPoser connector • Columns of silver-plated nickel particles uniformly distributed in a thin sheet of silicone • 0.50mm pitch • Thickness: 0.13mm • Voltage breakdown: 750V • Contact resistance: <25m • Current Carrying Capability: 1A • Little/no effect seen in company measurements: • Temperature cycling – 700 cycles, 20 – 100 C • Corrosive atmosphere for 100 hours A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  17. R&D of RCC, PariPoser • Solid FPGA soldering • The first version of flex-RCC • Fragility of flex circuit board • Eccobond (epoxy) to enforce finite curve to the bend • Bake (~80C/~30min) before bending the flex wings. • Flat alignment for the PariPoser connections • Thickness of the stiffener boards • Calculate precise length of wings • Production issues • AX125-CS180 chip production has been terminated. • Open via issue (after increase the thickness of stiffener boards) A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  18. Ladder data transfer board (LDTB) • Optic transceivers/SERDES chip • Data (up), Command (down), Clock (down) lines • FPGA: Actel AX-1000-FG484 • One time programmable • Passes through serial control data, and FEM commands that control Digitization and Readout. • Select the data phase (channel or ADC data, selected via serial control) and multiplex the six 8-bit RCC data busses onto one 16-bit bus operating at three times the speed. • Logic is triplicated. • Low-voltage regulators • For LDTB-FPGA, RCC-FPGA, SVX4 chips • Bias voltage (passive) • Connection to bus cable • Option for crystal clock (unused) A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  19. R&D of LDTB • Timing adjustment for 6 RCC data readout • 12.5ns sampling clock window • ~7ns delay at bus + <~2-3ns skew + unknown skew in FPGA • Extra delay when PariPoser resistance is unexpectedly high. • SERDES chip • TLK2501 (75-125MHz) for 9.4x8 GTM clock • No problem at 74.5MHz test • FPGA soldering • 16 layer special board sucks more heat then expected, and the lead free pads need more heat. • About half of FPGA are failed for the soldering at company A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  20. Bus cable • 4 layers (2 signals, power, GND), 25” length • 50 Ω impedance-matched lines, Resistor array to terminate bussed control lines • Fixed issues • Clock delay • Voltage drop across the bus cable • Solid LDTB/bus connection A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  21. FEM • One VME crate per half (West/East) • 1 Control Interface Board (CIB) • Mbit, slow control parsing • Propagate GTM clock to DIBs (thgouth VME Backplane) • Option for front-panel clock propagation (MMCX) • 20 Data Interface Boards (DIB) • 8 for layer 3, 12 for layer 4 • Send clock/command to the ladder. Send data to DCM. • PLL chip double/filter the GTM clock • Pedestal correction • Data and serial control data readback can be checked through DIB-USB standalone A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  22. Full Chain test and bit error rate • With the full chain test at BNL (Aug-Sep), we took found no bit error for 2M events. • 74688 bits per event  1.5 x 10^11 bits • With fast test (data loop from LDTB), we found that the bit error rate is less than 10^-14. • Multi buffer events are successfully taken up to 3 LVL1 burst, but not 4. • DCM issue (which is not expected 75k bits/event, and should be fixed with DCM2) • No data corruption which hanged up DAQ. • DIB-DCM communication is driven by local crystal. • Bit error rate with final setup is being investigated. 65m fiber x3 CIB DIB Mode bits GTM FPGA 4x9.4MHz 8x9.4MHz FPGA PLL 8x9.4MHz 4x9.4MHz Mode bits Backplane data-in data-out LMK3000 Glink card 80 MHz crystal TLK2501 DCM FPGA RCC ROC RCC ROC RCC ROC RCC ROC RCC ROC RCC ROC A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  23. Online pedestal correction • For zero-suppression, ADC values are corrected channel-by-channel for event-by-event at DIB before being sent to DCM. • Subtract the mean pedestal value which is calculated by averaging ADCs from 8 neighbor channels within truncation window. A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  24. Summary • All of the known issues have been solved for stripixel readout system. • All 40 ladders have been successfully installed and being checked now. • Run11 p+p Physics run is about to start, followed by Au+Au run starting in March. Keep your fingers crossed! A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  25. Backup slides

  26. The PHENIX detector • 2 central spectrometers • Tracking (DCH, PC, Magnet) • Identified hadrons (TOF, EMC timing) • , K, p, d •   KK,  p, etc. • Photons (EMC) • Direct photons • 0  • Electrons (RICH) • D, B  e+X • J/, ’, , ,   e+e- • Covered by VTX • 2 forward spectrometers • Muon tracker + indentifier • J/, ’  +- • D, B  +X • Covered by FVTX A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  27. Physics Goals for RHIC-PHENIX • Detailed investigation of the properties of the Quark-Gluon Plasma created in heavy ion collisions. • Nuclear modification functions (RAA) of high-pT hadrons, photons, di-leptons. • Direct photon spectra • Gamma-hadron jet correlations • Elliptic flow (v2) • Soft physics (single spectra, HBT, v2 of low-pT hadrons) • Fluctuations • Exploration of the nucleon spin structure in polarized p+p collisions • Transverse single and double spin asymmetries A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  28. VTX physics performance • B and D are embedded into PYTHIA. • Assuming the high DCA at low pT electron spectrum is dominant by D decays, obtain slope parameter (S0) from the measurement of DCA slope at low pT. • Fit the distribution of (DCA, pT) with two components, charm and bottom. • Parameterization defined by PYTHIA simulation studies are: • Scharm = 1.1 S0 pT0.1 , Sbottom = 1.1 S0 pT0.1/1.5 A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  29. FVTX overview • Matches acceptance of the muon arms • 1.2 < |h| < 2.4 (incl. VTX) • Z = 18.5 to 38.5 cm • Two endcaps • Four planes per endcap (3 “large” + 1 “small) A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  30. prompt pm FVTX physics performance • D, B mesons travel ~1 mm before decaying to muons. DCA measurements allow separation of prompt, D/B, /K decays. • Generate D, B and background events and mix them with a known fraction. • The b/(c+b) ratio was extracted from a sample which included c, b and background. A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  31. Pedestal correction algorithm • Step 1: Copy the ADC values of the first 8 channels into an 8‐bit FIFO that will be usedto calculate the mean. • Step 2: Calculate sum (S) of the ADC values stored in the FIFO (Ai), their mean (M,chop off lower 3 bits), and the differences (Di) between Ai and M. • Step 3: Identify any channels that have hits or are dead, by demanding the differencebe smaller than some threshold, |Di| < T. • Step 4: Replace (effectively) hit/dead channel ADC values in the mean‐calculator FIFOwith M. • Step 5: Recalculate M with hit/dead channel ADC values replaced, as described in Step 4, and recalculate/write out the differences (Di) between Ai and M for the first 8channels. • Step 6: Determine the appropriate mean value for the next channel, by (effectively)sliding the channel window covered by the mean‐calculator FIFO by one channel. ‐‐ Check the ADC value of the next channel to see if it is hit/dead. ‐‐ If it is, replace the A1 with M. ‐‐ If it is not, replace A1 with A9. • Step 7: Repeat step 6 until the last channel of the chip is reached. A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  32. Radiation length CF 410um ROC : 0.9mm width 80mm G10 1484um Cu 27um Kapton 127um Coolant H3C4OF7 Carbon Foam Al 381um Cu 54um Cu 27um G10 1484um Cu 27um Kapton 27um total 1 = 4.22 + (0.29+1.15)(overlap-RCC edge) = 5.66 (%) total 2 = 4.22 + (0.11+0.38)(overlap-RCC edge) = 4.71 (%) A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  33. Transfer speed • Tdigi – Time to digitize charge samples on SVX4: ~4 usec • Tfifo – Time to buffer data to allow continuous data transfer to the FEM: ~0.6 usec • Tped-corr – Overhead for pedestal correction algorithm: ~1 usec • Txfer – Time to transfer data from LDTB to FEM, or from FEM to DCM: ~58 usec • In order to minimize the required times, we will allow data transfer to the DCM to start before all data has reached the FEM. • Conversion time is the sum of Tdigi + Tfifo + Tped-corr ~5.6 usec: at this point the data is ready to transfer to the DCM. • ENDDAT time is Txfer + Tdigi + Tfifo +Tped-corr ~ 63.6 usec: at this point the second event is ready to transfer to the DCM. Tped-corr Tdigi Tfifo Txfer (1st event to FEM) Tped-corr Tdigi Tfifo Txfer (1st event to LDTB) Start digitizing 2nd event here Conversion time ENDDAT time Start FEM xfer of 2nd event here A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  34. Low-pT PID A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

  35. Digital Activity check (RMS) Digital activity doesn’t affect the RMS of pedestal corrected ADC distributions, as expected from previous studies. A. Enokizono - PHENIX Upgrade MiniWorkshop - RIKEN

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