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VHDL Project Specification

VHDL Project Specification. Naser Mohammadzadeh. Schedule. due date: Tir 18 th. Groups. One person. Honor Code Rules. Using somebody’s else code and presenting it as your own is a serious Honor Code violation and may result in an F ail grade for the entire course.

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VHDL Project Specification

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  1. VHDL Project Specification NaserMohammadzadeh

  2. Schedule • due date: Tir 18th

  3. Groups • One person

  4. Honor Code Rules • Using somebody’s else code and presenting it as your own is a serious Honor Code violation and may result in an Fail grade for the entire course. • All student teams are expected to write and debug their codes by themselves and are not allowed to share their codes with other teams. • Students are encouraged to help and support each other in all problems related to the • basic understanding of the problem • operation of the CAD tools

  5. Platform & Tools • Target devices: • Xilinx FPGA Virtex 7 family • Tools: • VHDL Simulation: ModelSim • VHDL Synthesis: Xilinx XST 14.6i or later • Implementation: Xilinx ISE 14.6i or later

  6. Final Deliverables • All block diagramsand ASM chartsdescribing the entire circuit and its components(electronic form, PDF) • All synthesizable VHDL source codes • All testbenches used to verify the operation of the entire circuit and its components, and the correspondinginput files containing test vectors, and output files containing results • Timing waveforms demonstrating the correct operationof the entire circuit and its components • Final report

  7. Final Report (I) • Short description of the block diagrams and ASM charts. Discussion of any alternative architectures and solutions. • List of source codes and a short description of major modules. • Source of test vectors and a way of generating these test vectors. • Format of input & output files.Short description of a testbench.

  8. Final Report (II) • Results • resource utilization (CLB slices, LUTs, FFs,BRAMs, etc.) • post-synthesis timing • clock frequency • throughput • latency • critical path • post placing & routing timing • clock frequency • throughput • latency • critical path

  9. Final Report (III) • Discussion of the obtained results and and any optimizations applied in order to obtain the optimum design. • Speed-up vs. software implementation. • Discussion of dependence of results on parameters of the application. • Deviations from the original specification, encountered problems, and unresolved issues.

  10. Main Project • Resource: • B. Parhami, “Computer Arithmetic, Algorithms and Hardware Designs,” 2000. (you can find it in “ftp://eng-ftp.sh.local/Professors/Mohammadzadeh-PhD -> Advanced Digital Design-> Resources”) • Projects: • Double Precision Floating Point Multiplier (Figure 18.5) • Structural

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