Xilinx CPLDs and FPGAs

1. Xilinx CPLDs and FPGAs Lecture L1.1

2. CPLDs and FPGAs • XC9500 CPLD • Spartan II FPGA • Virtex FPGA

3. 3 In-System Programming Controller JTAG Controller JTAG Port Function Block1 I/O I/O Function Block 2 I/O I/O Blocks FastCONNECT Switch Matrix I/O Function Block 3 Global Clocks 3 Global Set/Reset 1 Function Block 4 Global Tri-States 2 or 4 XC9500 CPLDs • 5 volt in-system programmable (ISP) CPLDs • 5 ns pin-to-pin • 36 to 288 macrocells (6400 gates) • Industry’s best pin-locking architecture • 10,000 program/erase cycles • Complete IEEE 1149.1 JTAG capability

4. Global Clocks Global Tri-State 2 or 4 3 I/O Macrocell 1 Product- Term Allocator AND Array 36 From FastCONNECT I/O Macrocell 18 To FastCONNECT XC9500 Function Block Each function block is like a 36V18 !

5. XC9500 Product Family 9536 9572 95108 95144 95216 95288 Macrocells 36 72 108 144 216 288 Usable Gates 800 1600 2400 3200 4800 6400 tPD (ns) 5 7.5 7.5 7.5 10 10 Registers 36 72 108 144 216 288 Max I/O 34 72 108 133 166 192 VQ44 PC44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 Packages HQ208 BG352 PQ160 HQ208 BG352

6. Xilinx 95108 • 6 function blocks • Each contains 18 macro cells • Each macro cell behaves like a GAL32V18 • AND-OR array for sum-of-products • 32 inputs and 18 outputs

7. Architecture of the Xilinx XC95108 CPLD

8. Controlled inverter Each Xilinx 95108 macrocell contains a D flip-flop

9. Each Xilinx 95108 macrocell contains a D flip-flop Note asynchronous preset x z y Note asynchronous reset

10. CPLDs and FPGAs • XC9500 CPLD • Spartan II FPGA • Virtex FPGA

11. Block diagram of Xilinx Spartan IIE FPGA

12. Each Spartan IIE CLB contains two of these CLB slices

13. Xilinx Spartan-II FPGAs

14. Block RAM

16. Delay-Locked Loop

17. Phase-Locked Loop

18. CPLDs and FPGAs • XC9500 CPLD • Spartan II FPGA • Virtex FPGA

19. Virtex FPGAs For info on Virtex 1000 boards, see http://www.zarx.info/

20. Virtex-II FPGAs

21. Virtex-II Pro FPGAs