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Pertemuan 3 Karakteristik Logik Gerbang MOSFET

Pertemuan 3 Karakteristik Logik Gerbang MOSFET. Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01. Learning Outcomes. Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menjelaskan karakteristik logik gerbang MOSFET. a = 0. a = 1. y. y. x.

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Pertemuan 3 Karakteristik Logik Gerbang MOSFET

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  1. Pertemuan 3Karakteristik Logik Gerbang MOSFET Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01

  2. Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menjelaskan karakteristik logik gerbang MOSFET.

  3. a = 0 a = 1 y y x x tutup buka Hubungan seri: a b a . 1 (a . 1) . b g = a . b 1 a Hubungan paralel: a . 1 b + b . 1 1 f = a + b Ideal Switch Assert-high

  4. a = 1 a = 0 y y x x Assert-low tutup buka Hubungan seri: a b a . 1 (a . 1) . b g = a . b 1 a a Gerbang NOT: f(x) = a . 1 + a . 0 Mux a . 1 1 1 0 a + a . 0 0 f = a . 1 + a . 0 = a Ideal Switch

  5. Gate Gate Simbol Source Drain Source Drain pFET nFET VDD VDD > 0 V + + + Logik 1 VDD - - - Ke chip Tak tentu VDD Rangkaian CMOS VSS Logik 0 0 VSS < 0 V Power supply Single voltage power supply Dual power supply voltages MOSFET Switch

  6. a = 0 a = 0 a = 1 a = 1 x x x x y = ? y = x y = x y = ? tutup buka tutup buka MOSFET Switch nFET pFET

  7. VA Ke VDD nFET VDD Drain Gate A = 1 Mn ON VA Mn + VGSn VTn Source - A = 0 Mn OFF VA VDD pFET VDD A = 1 Mp OFF Source VSGp + (VDD - |VTn|) - VA Mp Gate Drain Ke ground A = 0 Mp ON MOSFET Switch Threshold voltage

  8. MOSFET Switch VDD out in + + Vy = 0 V Vx = 0 V - - VDD VTn + - out in - + + |VTp| Vy = VDD - VTn Vx = VDD + - - out in out in + + + + Vx = 0 V Vy = |VTp| Vx = VDD Vy = VDD - - - - Pass Characteristics nFET pFET

  9. VDD 1 SWp output a f (a, b, c) Control block inputs b c SWn VSS 0 VDD 1 VDD 1 tutup buka a a f = 1 Control block inputs f = 0 b Control block inputs b c buka c tutup VSS 0 VSS 0 Gerbang Logik CMOS

  10. Ke VDD pFET Pasangan complement CMOS x Gerbang NOT nFET x x x x 0 1 1 0 Ke VSS Mn OFF Mn ON Mn VDD Ke VDD Mp Ke VDD X = 0 x x Mp Mp OFF Mp ON X = 1 Mn Ke VSS Ke VSS Gerbang Logik CMOS

  11. Gerbang NOR 0 1 A B A F Mux A B F 0 0 1 0 1 0 1 0 0 1 1 0 F = A + B 1 0 0 0 0 1 2 3 B VDD Mpx Mpy 1 . A . B F = A + B 0 . B Mny 0 . A Mnx B A Gerbang Logik CMOS

  12. 0 1 A B Mux Gerbang NAND F = A . B 1 1 1 0 0 1 2 3 A A B F 0 0 1 0 1 1 1 0 1 1 1 0 F B VDD Mpx 1 . A 1 . B Mpy F = A . B Mnx 0 . A . B Mny B A Gerbang Logik CMOS

  13. M N Fan-in M Fan-out N Gerbang Logik CMOS

  14. F F B B C C A A Gerbang Complex F = A . (B + C) = A + (B + C) = [A + (B . C)] . 1 = A . 1 + (B . C) . 1 VDD VDD 1 . A 1 . B . C B A F = 0 jika A = 1 AND (B+C ) = 1 0 . [A . (B + C)] C 0 . (B + C) F A 0 . [A . (B + C)] F = A . 1 + (B . C) . 1 C A B B C A C B Gerbang Logik CMOS

  15. 1 time  1 time 0 T  2T    Blok 2 Blok 1 Blok 3 Clock dan Aliran Data System clock Block level system timing diagram

  16. RESUME • Ideal Switch: assert high, assert low. • MOSFET Switch: nFET, pFET. • Gerbang logic CMOS. • Clock dan aliran data.

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