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ITRS Design TWG

ITRS Design TWG. Logic/Circuit/Physical Issues. Table: Microprocessors. Test. Design Process. System-Level Design. Functional Verification. Logic/Phys/ Circuits. signal integrity (coupling cap. Delay and noise) inductance (self + mutual coupling) IR drop/ Ldi/dt in power bus

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ITRS Design TWG

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  1. ITRS Design TWG Logic/Circuit/Physical Issues

  2. Table: Microprocessors Test Design Process System-Level Design Functional Verification Logic/Phys/ Circuits • signal integrity (coupling cap. Delay and noise) • inductance (self + mutual coupling) • IR drop/ Ldi/dt in power bus • interconnect delay (buffer insertion) • clocking schemes/clock skew • electromigration in signal lines/power • frequency/power/current draw near-term (>100nm) long-term (<100nm) criticality

  3. Table: ASIC Test Design Process System-Level Design Functional Verification Logic/Phys/ Circuits near-term (>100nm) • predictive capabilities in front-end • physical-effects based floorplanning and block placement (IR drop, electromigration, interconnect delay) • new synthesis technology with physical effects included (in wireload models) • better TV with coupling delay included • better power estimation • signal integrity aware routing • signal integrity aware technology mapping (buffer-size selection) • incremental design flow (extraction, ECO) • statistical verification long-term (<100nm) criticality

  4. Table: Analog/Mixed-Signal/RF Test Design Process System-Level Design Functional Verification Logic/Phys/ Circuits • statistical variations (matching) • thermal gradients • lower power supply • multiple power supplies • substrate noise • transistor modeling • power supply noise near-term (>100nm) long-term (<100nm) criticality

  5. Table: System-on-a-chip Test Design Process System-Level Design Functional Verification Logic/Phys/ Circuits near-term (>100nm) • analog IP creation (hard cores only in target technology) • legacy IP reuse (how do we enable the use of old IP) • need to create a flow for reusable IP authoring • need to create a flow for SoC Design (platform-based design, IP integration, verification, ECO) • need to have multiple views of an given IP to carry out various types of verification/analysis • reuse of 3rd-party IP requires standards in bus protocol/structure • need to address embedded software long-term (<100nm) criticality

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