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The 2004 ITRS Assembly and Packaging Roadmap Joe Adam TWG Co-Chair

The 2004 ITRS Assembly and Packaging Roadmap Joe Adam TWG Co-Chair. Ryo Haruta – Renesas Dan Evans – Palomar Tech Enboa Wu – ITRI/NTU Shoji Uegaki – Kyocera Kuniaki Takahashi – Toshiba Hisao Kasuga – NEC Coen Tak - Philips Mark Bird - Amkor Bill Bottoms - 3MTS

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The 2004 ITRS Assembly and Packaging Roadmap Joe Adam TWG Co-Chair

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  1. The 2004 ITRS Assembly and Packaging Roadmap Joe Adam TWG Co-Chair

  2. Ryo Haruta – Renesas Dan Evans – Palomar Tech Enboa Wu – ITRI/NTU Shoji Uegaki – Kyocera Kuniaki Takahashi – Toshiba Hisao Kasuga – NEC Coen Tak - Philips Mark Bird - Amkor Bill Bottoms - 3MTS Steve Adamson - Asymtec Chi Shih Chang – SMS Bill Chen – ASE Mahadevan Iyer - IME Bernd Roemer - Infineon Henry Utsunomiya – ICT Jurgen Wolf – IZM Joe Adam – Skyworks Rainer Kyburtz - ESEC Jack Fisher - IPC George Harman – NIST Chuck Woychik – Plexus Sanjay Dandia – Philips Keith Newman – Sun Key Packaging Chapter Contributors

  3. Near Term Industry Challenges • We need to close the gap between semiconductor interconnect density and next level substrate density • Both Organic and Ceramic substrate density is improving but not as fast as silicon I/O density • Higher temperature capability to support lead free solder in high density organic substrates • Low cost embedded passives • The impact of BEOL and Cu/low K on packaging • Direct wirebond to Cu or improved barrier systems for bondable pads • Improve interfacial adhesion of dielectrics • Integrated fab/packaging process development, reliability, and test criteria to identify and resolve interaction problems early in the technology development cycle

  4. Near Term Industry Challenges • Tools and methodologies to address chip and package co-design • More efficient mixed signal co-design and simulation for chip and package within the same environment RF requirements • More accurate thermal and mechanical simulation of complex package microstructures, including materials data • Assembly equipment productivity is not improving fast enough to meet package cost improvement requirements • Reliability degradation due to electromigration in lead free and other package metallurgies

  5. Long Term Industry Challenges • Small high frequency, high power density, high pin count die • Very high chip I/O density which require reliable bumpless connections to meet thermal and electrical performance requirements • New devices and materials (organic, MEMS, nanostructures, optical, biological) which require new packaging technologies • System level design capability to integrate semiconductor, passive, interconnect and new device technologies in 3 dimensions • 450 mm wafer technical issues ( thinning, wafer level packaging, etc.)

  6. Subcontract Package Cost Trends

  7. System In Package Technology Requirements

  8. Package Materials Requirements

  9. Package Materials Requirements

  10. Die to Package Interconnect Requirements

  11. Crosscut issues • BEOL and low K/Cu integration into packaging • Wafer Level packaging impact on interconnect • Thinned die issues (test, FEOL) • New device types and structures impact on packaging • Design and Simulation (SIP, RF, etc.)

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