The 2003 ITRS Assembly and Packaging Roadmap Joe Adam TWG Co-Chair

1. The 2003 ITRS Assembly and Packaging Roadmap Joe Adam TWG Co-Chair

2. Ryo Haruta – Hitachi Dan Evans – Palomar Tech Enboa Wu – ITRI Shoji Uegaki – Kyocera Kuniaki Takahashi – Toshiba Hisao Kasuga – NEC Coen Tak - Philips Mark Bird - Amkor Bill Bottoms - 3MTS Steve Adamson - Asymtec Ted Zarbuck - Intel Chi Shih Chang – Bill Chen – ASE Greg Hotchkiss – TI Ed Fulcher - LSI Mahadevan Iyer - IME Bernd Roemer - Infineon Henry Utsunomiya – ICT Jurgen Wolf – IZM Joe Adam – Skyworks Rainer Kyburtz - ESEC Alex Oscilowski Jack Fisher - IPC George Harmin – NIST Mike Varnou – Delphi Yuji Shirai – ASET Michio Sono - Fujitsu Key Packaging Chapter Contributors

3. Assembly and Packaging Major Update Issues • Product sectors changed based on new market structure • A new difficult challenge in System In Package • Three new requirement tables being added on Substrate Technology, System In Package, Materials • Cost per pin number increased in low end products • Change in the power being made from max watts to watts/cm2 • Frequency tables being split into digital and RF based on inputs from PIDS and Design TWGS • RF will be based on carrier frequency • Digital will be based on clock

4. New Market Sectors • Low cost/hand held/memory - <$300 consumer products • These were consolidated based on coomon market requirements • Cost performance <$3000 notebooks, desktop • High performance >$3000 workstations, servers, network switches • Harsh - Under the hood, and other hostile environment

5. Difficult Challenges Near Term • Tools and methodologies to address chip and package co-design • Mixed signal co-design and simulation (SI, Power, EMI) • For transient and localized hot spots - simulation of thermal mechanical stresses, thermal performance and current density in solder bumps • Improved Organic substrates • Increased wireability and dimensional control at low cost • Higher temperature stability and lower moisture absorption • TCE and Modulas better matched to low K flip chip requirements • Improved underfills for flip chip and encapsulations • Improved underfill integration, adhesion, faster cure, higher temperature • Improved encapsulation and molding materials for SIP and Wafer scale packages • Impact of Cu/low k on Packaging • Direct wire bond and UBM/bump to Cu to reduce cost • Lower TCE and modulus substrates to reduce die level stress in flip chip • Lower strength in low k which creates a weaker mechanical structure

6. Difficult Challenges Long Term • Package cost may exceed die cost • Present R&D investments do not address this effectively • System level view to integrate chip, package, and system design • Design will be distributed across industry specialist • Small high frequency, high power density, high pin count die • Die sizes well below 1mm with multiple watts and several hundred I/O • Increasing gap between device, package and board wiring density • Cost of high density package substrates will dominate product cost • Global interconnect shift to packaging will be limited by size of this gap

7. Packaging Near Term Requirements

8. Packaging Near Term Requirements

9. Die to Package Interconnect Requirements

10. Die to Package Interconnect Requirements

11. Crosscut issues • Modeling of thermal and mechanical issues at package and device level which impact interconnect, test, design, modeling groups • Stress transfer from package to device level • Handling of lower strength low k dielectric structures • Materials properties are not available for many applications • Device performance skew due to temperature differences that are driven by package design and system applications • SIP drives changes in test, reliability, and design requirements