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LVDS 280MHZ link SPD VFE  PS VFE

LVDS 280MHZ link SPD VFE  PS VFE. Cable pre-selection. Cable model. Eye diagrams. Bit Error Ratio (BER) measurements. Summary. BCN – CFD-BCN meeting – 10/10/2003. I. Cable pre-selection. Several cat7 and cat6 SSTP cables will be tested:

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LVDS 280MHZ link SPD VFE  PS VFE

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  1. LVDS 280MHZ link SPD VFE  PS VFE • Cable pre-selection. • Cable model. • Eye diagrams. • Bit Error Ratio (BER) measurements. • Summary. BCN – CFD-BCN meeting – 10/10/2003

  2. I. Cable pre-selection. • Several cat7 and cat6 SSTP cables will be tested: • Infra+ cat7 patch cable (flexible) (datasheet) • Infra+ cat7 vertical cable (rigid)* (datasheet) • Infra+ cat6 vertical cable (rigid)*? • Nexans (Alcatel) cat7 patch cable ()* (datasheet) • Cat5e? Xtalk? Skew? • Cat7 rigid cable seems to have the better specs on skew and bandwidth. • Problems with rigid cables: • Section too big? • Cost? • Perhaps it is not possible to mount RJ45 connectors on cat7 rigid cable. Solution: MiniC connector, solder to boards ... (Infra+ connectors).

  3. II. Cable model. • RLGC model of cable (Theory of twisted pair cables). • Skin effect and dielectric looses limit the bandwidth. • How to simulate the cable response? Hspice W-model: how to calculate the cable parameters? • How to tune the compensation network? First order model for cable like in (High Speed Links for ATLAS).

  4. III. Eye diagrams. • Needed to validate the link within std LVDS levels. • Test equipment requirements: • BW  3 * 0.35/trise ( 1 GHz) for trise of 1ns. • Sampling rate  4 * BW ( 4 GS/s) (for proper reconstruction a a DSO) • Differential probe LAL measurement for DS90CR483/484 chipset

  5. III. Bit Error Ratio (BER) measurements. • Several test patterns will be used (miming IEEE 802.3 std): • High Frequency. • Low Frequency. • Deterministic jitter. • Random test pattern. • Test pattern (8K per bit) will be generated on a PC and transmitted to Cyclone or Stratix (Altera) Dev. Board operated at 40MHz to continuously check for errors. • Automatic synchronization for different cable lengths (cycle and phase) • 10 bit error counter bit will be enough? • Needed to identify the word of the frame when when error happens? • It is possible to generate pseudo-random test pattern with a LFSR register. • References: ATLAS-LEB2000 and VELO-LHCb.

  6. IV. Summary. • Several cable will types and lengths (from 10m to 30m) will be tested. • The first step is to characterize the cable and tune the compensation network for each type of cable and length. • After reducing the candidates extensive BER measurements will be performed. • Sensitivity to the jitter of 40 clock of the serializer needs to be tested, since is supplied through a 25 m cable from Control Board. • Performance of PIN diode level shifter (before serializer) will also be tested. • Possible level shifter in LVDS link will be tested (at 280MHz!)

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