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A Mixed-Signal CMOS VLSI Image Convolution Circuit using Error Spectrum Shaping

A Mixed-Signal CMOS VLSI Image Convolution Circuit using Error Spectrum Shaping. Brent Buchanan. July 2001 School of Electrical and Computer Engineering Georgia Institute of Technology. y[n, m] =  x[n-k, m-l]h[k, l]. h. k,l. y. x. Analog Multiplier. Weight. Data. e d. e w. e m.

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A Mixed-Signal CMOS VLSI Image Convolution Circuit using Error Spectrum Shaping

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  1. A Mixed-Signal CMOS VLSI Image Convolution Circuit using Error Spectrum Shaping Brent Buchanan July 2001 School of Electrical and Computer Engineering Georgia Institute of Technology

  2. y[n, m] =  x[n-k, m-l]h[k, l] h k,l y x Analog Multiplier Weight Data ed ew em From Other Multipliers S ObjectiveDevelop and demonstrate a CMOS VLSI architecture for performing general image convolutions using Error Spectrum Shaping Circuit’s Spatial Noise Model Discrete 2-D Convolution

  3. Current Mirrors Resistive Sheets E.g., Mahowald’s Silicon Retina To Neighboring Pixels From Neighboring Pixels Variable Pixel Response E.g., Funatsu’s Variable Sensitivity Photodetectors Iout Analog-Computation Convolutions

  4. ‘Disposal’ Band p p Sampled Image N-bit Quantized 2x Sampled Image N-bit Quantized p Sampled Image Perfect Intensity Resolution Oversampling Signal Band Image Spectrum Quantization Noise Spectrum Total Binary Quantization Noise Energy = f(N) 3 dB reduction in Quantization Noise per Doubling of Sampling Rate W. R. Bennett, “Spectra of Quantized Signals,” 1948 Example: 8-bits/sample at 4x Nyquist  6dB in-band improvement  9-bits/sample at Nyquist

  5. 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 p p 2x Sampled Image N-bit Quantized 2x Sampled Image ESS N-bit Quantized 5 5 5 5 5 6 5 6 5 5 5 5 5 6 5 7 e e h(ti) hq[ni] Error Spectrum Shaping Quantization Noise Spectrum ‘Disposal’ Band Image Spectrum hq[ni] h(ti) e Binary Quantization or other Representational Inaccuracy f(zi)

  6. y[n, m] =  x[n-k, m-l]h[k, l] k,l Analog Multiplier Weight Data ed ew em From Other Multipliers S Convolution and Noise Model Circuit’s Spatial Noise Model Discrete 2-D Convolution

  7. Quantization Examples 5122 x 1-bit Simple Quantization ESS Quantization

  8. Signal-Noise Ratio 10 Log [sij2/(yij – sij)2] Space Based SNR |x[n]|2 = 1/N  |X(n)|2 Parseval’s Relation 10 Log [|Sij|2 / |Yij – Sij|2] Spectrum Based SNR Total in-band noise (dB) vs signal bandwidth 3-bit Lenna 5122, 10242, 20482 images Binary Quantization Noise

  9. Random Gaussian Noises = 12.5% Full Scale Additive Noise ESS

  10. Difference of Gaussians Bandpass Filter 1st Order ESS 1-Bit DOG Ideal

  11. Convolution w/Corrupting Elements Binary Quantization Noise: 3-bit 2nd order ESS 642 DOG with 3-bit 2nd order ESS 10242 image 3-bit Binary Quantization Ideal result: floating point 642 DOG with 8-bit 10242 image Random Gaussian Noise s = 12.5% FS

  12. Data Data Data Data Data Data Data Data Data Weight Weight Weight Weight Weight Weight Weight Weight Weight MDAC MDAC MDAC MDAC MDAC MDAC MDAC MDAC MDAC Summing Nodes Control Data Bus The Architecture Analog Multiplications Digital Data & Weight Registers Positive & Negative Summing Nodes (extendable to Complex) Kernel Sample Instantiations: Convolution Kernel Support and Pipelining Patterns 2-D 1-D Signal

  13. P-Channel I Sources Divide by 4 Mirror P Balance 1/4x 1/4x 1/2x W1 W0 D2 D3 D4 1x 2x 4x Weight DAC N-Channel I Sinks Iout Data DAC Ibias W3 D1 W4 D0 W2 1x N Balance MDAC Schematic

  14. Node Switch Weight DAC Data DAC Memory Cell 56 l 181l MDAC, 6-Bit Sign/Weight Register, and Output Switch MDAC Layout Digital Equivalent Circuit Analog MDAC Cell Area Alone 1:69 1:338 3LM Actual 1:83 Routed in 5 Layer Metal (Theoretical) Analog vs Digital Relative Area Comparisons

  15. Measured Results I: Single MDAC Chip #8, MDAC at Row 0 Column 0

  16. Increasing Data Word Increasing Output Current Increasing Weight Word Increasing Row Index Increasing Column Index Focus Portion of Array Measured Results II: Array MDACs 0 - 200 mA Chip #8, MDACs in Rows 0-4 & Columns 0-4

  17. Error Distribution D1 D0 D2 D3 D4 Data Bits Maximum Outputs

  18. Variance vs Location

  19. MDAC-Fit DOG Filter MDAC Array-Specific 1st Order ESS Ideal

  20. DOG Convolution Results • MDAC-based result: 642 MDAC array-specific 1st order • ESS DOG convolved with 10242 1-bit 1st order ESS image Ideal result: floating point 642 DOG convolved with the 8-bit 10242 image

  21. Total In-band Noise for selected MDAC-based convolutions Chip #8, middle center-band DOG

  22. Total In-band Noise Measured at 1282 Chip #8

  23. Conclusion ESS demonstrated to successfully displace noise inherent in CMOS VLSI computational arrays Crude ESS algorithms Assumption about noise in Current-mode summation Future Directions Multidimensional ESS/SD APS CMOS Imager Pipelined Convolution Processor Fast MPEG encoder

  24. Publications THESIS RELATED B. Buchanan, M. Brooke, “ Error Spectrum Shaping in Analog Image Convolution Circuits“, Submitted to IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications B. Buchanan, M. Brooke, “A Mixed-Signal Image Convolution Circuit using Error Spectrum Shaping “, Submitted to IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing B. Buchanan, M. Brooke, “Analog CMOS Image Convolution Circuitry using Error Spectrum Shaping,” Proceedings of Philips Research 10th Seminar on Analogue and Mixed-Signal Design, Eindhoven, Netherlands, June2001 OTHER B. Buchanan, “IC Cell and Library Identification”, Application for United States Letters Patent, Filed 29 June 2001 B. Buchanan, V. Madisetti, M. Brooke, "Performance of a Fast Analog VLSI Implementation of the DFT", Proceedings of the 35th Midwest Symposium on Circuits and Systems, Vol 2, pp 1353-6, August 1992 B. Buchanan, C. Camperi-Ginestet, T. Morris, M. Brooke, S. DeWeerth, N. Jokerst, M. Allen, "High Density Focal Plane Signal Processing Using 3-D Vertical Interconnects", Proceedings of the 37th Midwest Symposium on Circuits and Systems, vol 1, pp 191-4, Aug 1994 C. Camperi-Ginestet, B. Buchanan, Y. Wang, N. Jokerst, M. Brooke, M. Allen, "Three Dimensional Smart Pixel Integration of a GaAs-Based Detector Array Directly on Top of Silicon Circuits", LEOS Summer Topical Meetings 1994: Smart Pixels, pp 56-8, July 1994 C. Camperi-Ginestet, B. Buchanan, S. Wilkinson, N. Jokerst, M. Brooke, "Integration of InP-Based Thin Film Emitters and Detectors Onto a Single Silicon Circuit", Optical Society of America 1995 Spring Topical Meetings , March 1995, Salt Lake City, Utah D. S. Wills, W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, H. H. Cat, S.T. Wilkinson, M. Lee, N. M. Jokerst, M. Brooke, "A Three-Dimensional High-Throughput Archtecture Using Through-Wafer Optical Interconnect", IEEE-OSA J. L. T., vol 13, pp 1085-92, June 1995 J. Cross, A. Lopez-Lagunas, B. Buchanan, L. Carastro, S. C. Wang, N. M. Jokerst, S. Wills, M. Brooke, M. A. Ingram "A Single-Fiber Bidirectional Optical Link Using Colocated Emitters and Detectors", IEEE Photon. Tech. Lett., vol 8, no 10, pp 1385-7, Oct 1996 N. M. Jokerst, M. Brooke, O. Vendier, S.T. Wilkinson, S.M. Fike, M. Lee, B. Buchanan, D. S. Wills, A. Brown, "Manufacturable Mult-Material Integration Compond Semiconductor Devices Bonded to Silicon Circuitry", SPIE, 1995 N. M. Jokerst, M. Brooke, O. Vendier, S.T. Wilkinson, S.M. Fike, M. Lee, E. Twyford, J. Cross, B. Buchanan, D. S. Wills, "Thin Film Mult-Material Optoelectronic Integrated Circuits", IEEE Trans. on Comp. Pack. and Man. Tech. Part B., vol 19, no 1 pp.97-106, Feb 1996 N. M. Jokerst, C. Camperi-Ginestet, B. Buchanan, S.T. Wilkinson, M. Brooke, "Communication Through Stacked Silicon Circuitry Using Integratged Thin Film InP-based Emitters and Detectors", IEEE Photon. Tech. Lett., vol 7, pp 1028-30, Sept 1995 S. M. Fike, B. Buchanan, N. Jokerst, M. Brooke, T. Morris, S. DeWeerth, "8x8 Array of Thin-Film Photodetectors Vertically Electrically Interconnected to Silicon Circuitry", IEEE Photon. Tech. Lett., vo7, no 10, Oct 1995 W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, M. Lee, S. Wilkinson, D. S. Wills, N. M. Jokerst, M. Brooke, "A Fine-Grain, High-Throughput Architecture Using Through-Wafer Optical Interconnect", Special Issue of the Journal of Light. Tech., Jan 1995 W. S. Lacy, M. Grossglauser, C. Camperi-Ginestet, B. Buchanan, D. S. Wills, N. M. Jokerst, M. Brooke, "A Fine-Grain, High-Throughput Architecture Using Through-Wafer Optical Interconnect", Proceedings of: Workshop on Massively Parallel Processing Using Optical Interconnections, April 1994, Cancun, Mexico

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