Summary of Thermal Studies of L-Shape Module

1. Summary of Thermal Studies of L-Shape Module Steven Blusk, Brian Maynard Syracuse University Velo Upgrade Workshop, Module 0, May 5, 2010

2. Introduction • Thermo-mechanical issues • Keep silicon safely away from the point at which it will thermal run away. • Minimize thermal gradient across module • Mechanical deformation, internal stresses, bi-metallic effects, etc. • Here, I will focus on L-shape design, as this is favorable from a physics perspective. • Thermal modeling using ANSYS • Focus for today • Should mention we did compare some simple thermal simulations with analytical calculations, and they agreed.

3. L-Shape Geometry Ray Mountain, 3-24-2010 1 2 3 In ‘diamond option’diamond detectorsclose to IP, underneathchips 4, 5, 7, and 9. 4 5 6 7 8 9 10 11 12

4. Basic “Agreed-on” Parametersrelevant for thermal analysis • Substrate Thickness: 200 mm • Diamond assumed for now. • Silicon thickness: 150 mm • Chip: • Size: 14.1 mm x 14.1 mm (+ 1 mm for digital back end.) • Total chip power < 3 W/chip • Analog Pixel Power: < 1.3 W/chip. (15-20 mW/pixel) •  Digital power < 1.7 W/cm2 (in pixel vs backend ?)

5. Materials in the “Sandwich” Silicon 0.150 ASIC 0.150 Epoxy 0.050 Al 0.050 Substrate 0.200 All dimensions in mm Very small sensitivity to using slightly different values.

6. Cooling Channel Placement Cooling Channel 1.0 cm Drawing complimentsof R. Mountain Obvious, this isnot a “real” coolingchannel, but basicallyfixes the temperatureat a fixed distance fromsilicon edge. 1.5 cm NB: 50 um of gluebetween cooling channel & substrate

7. Power Contributions - Silicon Silicon self-heating (at 1x1016 neq/cm2,900 V) Radial & temperature dependent power dissipation in silicon Beneficial annealing reduces current by ~ 40%, and is included in

8. Power Contribution - Chip Power Digital Power in Backend of chip (PD) : PD: Vary from 0.5 to 2.5 W/chip Analog power in pixel cells. Assume 2 contributions. 1 2 3 • PA = Constant analog pixel powerVary from 0.5 to 1.5 W / chip • Radial dependent power (Pr)Occupancy-dependent power (?)Pr= Kp (7.5 mm/r) (vary Kp from 0.5 – 2.5) 4 5 6 7 8 9 10 11 12 Total Pr vs Chip #

9. Methodology • Fix cooling channel at -35 C • Fix the Analog Power, PA (say 0.5 W/chip) • Vary digital back end power, PD and radial-dependent power, Pr. • Record highest temperature of silicon. • Make ‘highest temperature table’ for PD vs Pr • Repeat step 2 for 1.0 W/chip and 1.5 W/chip

10. Results

11. PA = 0.5 W/chip ‘Dash’ meansThermalRunaway Table shows the highest temperature of the silicon sensor. PD (W/chip) KP 50

12. PA = 1.0 W/chip Table shows the highest temperature of the silicon sensor. PA=1.0 W/chip PD=1.5 W/chip Pr ~ 0.2-0.5 W/chip PD (W/chip) KP 50

13. PA = 1.5 W/chip Table shows the highest temperature of the silicon sensor. PA=1.5 W/chip PD=1.5 W/chip Pr ~ 0.2-0.5 W/chip PD (W/chip) KP 50

14. Thermal Profile – “Low Power” Scenario Note that upper & lower half not exactly symmetric with respect to distance tocooling channel(see slide 6) “Low power”scenario PA=0.5 W/chip PD=0.5 W/chip kP=0.5

15. Thermal Profile – “High Power” Scenario “High power”scenario PA=1.5 W/chip PD=1.5 W/chip kP=1.5 Not a whole lot of headroom if chip is near theupper end of the spec. Should try very hard tokeep chip power “wellbelow” the spec. value.

16. Summary (1) • For chip power close to maximum values in Timepix2 specs (see talk by Xavi Llopart here), silicon approaches ~ -5 C, close to runaway.. • If no radial dependent power (Pr=0), gain 1-2 C. • Critical to keep power to a minimum. • This assumes we can deliver -35C to cooling channels.. Can an upgraded CO2 cooling system achieve this????

17. Summary (2) Other tests performed & considerations • Splitting top 6 chips and bottom 6 chips give comparable thermal performance to full module (to within 1 C) • Thicker diamond substrate 200 mm400 mm would give about ~2-3 C lower temperature. (Diamond not bottleneck) • Could move cooling channel closer than 1.5 cm (or 1.0 cm) along the one edge? Would help a bit.. • Moving further away would have significant consequences. • ‘Diamond option’ would certainly help thermally: • In “low power” scenario, Tmax decreases -24.6 C  -25.2 C • In “high power” scenario, Tmax decreases ~ -3 C  -9 C • Simulations for dose of 1.0x1016 neq/cm2 (~100 fb-1) • If only 50 fb-1, then half the dose, lower silicon power loss. • Need head room! Some possible small gains or losses having to do with glue conductivity, thickness, other heat loads, etc.

18. Summary (3)Questions • Real estate availability for cooling channel and readout cables from chips? • How close can we get the cooling lines? • Any idea what the readout cables will look like? Cu-Kapton flex? • Tube should be low profile, squished down.The ‘art of tube squishing’. • Possibly thermal “fingers” instead of tubes? • How cold can we get with upgraded cooling plant?

19. Plans • Armed with these tools and detailed simulations, we’d like to construct a mechanical mock up (starting this summer) • Substrate, 2 silicon layers, glue, heaters, cooling, RTDs, etc • Measure thermal profile (in vacuum), and compare to ANSYS simulation of the mechanical model. • Also thinking about modeling the thermal stresses and mechanical deformations.