Outline

1. Outline • Lab 4 - solution to questions in prelab • Lab 5 - 8bit counter with non-debounced and debounced clock • Lab 6 - introduction

2. 7-seg display a X0 b X1 c X2 d X3 e f g 7-seg display • Four inputs • Seven outputs • Seven separate functions/schematics inside, each corresponding to a single segment/LED

3. 8bit Counter Inputs: LDN: Set to H A – H: Set to L GN: L -> counting normally DNUP: Set to L to count up SETN: Set to H CLRN: Connect it to a switch, so that you can manually clear the counter CLK: feed it with the rising clock edges generated by button(s) Outputs: QA – QD: low-order digit, to 7-seg display driver QE – QH: high-order digit, to 7-seg display driver COUT: unused

4. 7-seg display 7-seg display a a X0 X0 b b X1 X1 c c X2 X2 d d e X3 X3 e f f g g Designs 1 and 2 GND VCC RS Latch

5. Input CLK Tips • Make sure your 7-seg display works • Construct your own RS flip-flop or use system’s RSFF • When you compile your file, if “global clock error” messages is displayed, please add one AND gate depicted below between your push button (use them to generate clock) and the CLK inputs of counter and RS flip-flop.

6. To-do list • Turn in the prelab report • Not necessary to create the simulation files • Implement the two designs by using MAX+plus II • You don’t need to • Demonstrate the above three designs to the TA • Zip the .gdf files. Email me the zip file. • Make sure I give you credit before you leave the lab.

7. Lab 6: 4bit Shift Adder Inputs: Three control inputs: ST: Shift LD: Load (from A,B,C,D) CLRN: Clear SER: New value that is shifted into reg. Outputs: QA: MSB) QD: LSB

8. 4bit Shift Addition Clock Cycles Load A and B The carry-out of the full adder in the current clock cycle should be fed back to carry-in in the next clock cycle. Use D Latch to get the one-clock-cycle delay.

9. System Diagram one full adder, three/two shift regs., one D latch, 7-seg display