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Class Presentation on Binary Moment Diagrams by Krishna Chillara Base Paper: “Verification of Arithmetic Circuits using Binary Moment Diagrams ” by Randal E. Bryant and Yirng-An Chen. Outline. Introduction Binary Moment Diagrams (BMDs) MTBDDs, BMDs *BMDs - Illustration

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  1. Class Presentation onBinary Moment DiagramsbyKrishna ChillaraBase Paper: “Verification of Arithmetic Circuits using Binary Moment Diagrams” by Randal E. Bryant and Yirng-An Chen

  2. Outline • Introduction • Binary Moment Diagrams (BMDs) • MTBDDs, BMDs • *BMDs - Illustration • Construction rules of *BMDs • Boolean functions using *BMDs • Word level Operations using *BMDs • Verification using *BMDs • Summary

  3. Introduction • Some function representations discussed in this course • Sum of the Product form • Factored forms • Truth Table • Binary Decision Diagrams • Binary Decision Diagrams • Simple in representing and manipulating Boolean functions • Reduced Ordered BDDs are canonical (useful for verification) • Drawbacks of BDDs • Does not handle functions with non-Boolean range • Bit level representation but specs are in word level • Not good in terms of memory for multiplications • Consider a 32 bit multiplication using BDDs M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

  4. Shannon Expansion • Boolean function f decomposed in terms of a variable x can be represented by Shannon expansion as f = x fx + x’ fx’ • Function decomposed into positive and negative co-factors at the node variable x • fx = f(x=1) • fx ’ = f(x=0) • Point-wise decomposition

  5. Binary Moment Diagrams (BMDs) • Modified Shannon Expansion • Boolean variable treated as a binary (0,1) integer variable • Complement of x modeled as (1-x) • Now the function can be represented as f = x fx + x’ fx’ = x fx + (1-x) fx’ = fx’ + x (fx - fx’ ) = fx’ + x fx • Function is branched into two components • Constant Component (Negative co-factor) • Linear Component • Comparison with shannon expansion for Boolean M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

  6. Binary Moment Diagrams (BMDs) from truth table • For variable y, • y = 1 is encoded as y • y = 0 is encoded as (1-y) • With this encoding, linear expression can be directly obtained from the truth table Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

  7. Representation with MTBDDs and BMDs • MTBDDs • Multi Terminal BDDs • Extending BDDs to allow numeric leaf values • Point-wise decomposition based on Shannon expansion • BMDs • Linear moment decomposition • Dotted node represents constant moment and solid line represents linear moment Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

  8. Multiplicative BMDs (*BMDs) • BMDs simply encode the numerical values into terminal vertices. • In *BMDs edge weights are used to share any common sub-expressions. • *BMDs • Not decision diagrams as they are based on the moment decomposition • Multiplicative diagrams – each path is a product of nodes and the edge weights • Function is evaluated by adding all the encoded paths like in BDDs

  9. BMD reduction rules • Irredundancy • When a linear moment of at a node v is 0, the function has only a constant term and thus does not depend on ‘v’. • Hence node ‘v’ can be removed. • Merge the duplicates • Similar to BDDs • Two nodes with same index variable and having same two moments can be merged. M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

  10. Normalization of weights • Rules imposed on manipulating edge weights to make the graph canonical • Normalized by factoring out gcd of the argument weights w=gcd(wl(x),wh(x)) Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

  11. x y y z z z -20 12 24 15 4 2 8 Illustration • f=8-20z+2y+4yz+12x+24xz+15xy • Variable order (say) x,y,z • f= fx’ + x fx • Linear = fx • Constant = fx’ 8+2y+4yz-20z 12+15y+24z 8-20z 12+24z 4z+2

  12. x y y z z z -5 1 2 1 2 2 5 Illustration • f=8-20z+2y+4yz+12x+24xz+15xy • Variable order (say) x,y,z • Introducing the edge weights 8+2y+4yz-20z 12+15y+24z 2 3 4+y+2yz-10z 4+5y+8z 4-10z 8z+4 2 4 2z+1 2-5z 2z+1

  13. x y y z z 1 Illustration • f=8-20z+2y+4yz+12x+24xz+15xy = 8-20z+2y (1+2z) + 12x(1+2z) +15xy • Variable order (say) x,y,z • *BMD after reduction 2 3 4+y+2yz-10z 4+5y+8z 2 4 2-5z 5 2z+1 2 -5 2

  14. BMD *BMD x0 x1 x2 x3 8 4 2 0 2 0 8 4 1 1 x2 x1 x0 x3 1 Illustration BMD and *BMD • Unsigned integer: X = 8x3 + 4x2 + 2x1 + x0 Slide taken from Prof. Ciesielski’s TED presentation.

  15. Representation of Integers • Unsigned – sum of the weighted bits • Signed – Two’s complement, Sign-Magnitude Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

  16. y x y x y x y y x 0 1 0 0 1 1 1 Representation of Boolean Logic • NOT : x’ = (1-x) • AND: x.y • OR: x+y-(x.y) • XOR: x+y-2(x.y) -1 -1 -2 NOT AND XOR OR M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

  17. 0 1 y0 x0 y1 x1 y2 x2 Representation of word level operations - Addition • SUM X+Y • Both X and Y here are 3 bit wide • X= 4x2+2x1+x0 Y= 4y2+2y1+y0 • X+Y = (4x2+2x1+x0)+(4y2+2y1+y0) = 4*(x2 +y2) + 2*(x1 +y1) + (x0 +y0) • Linear with n- #bits • Why is it called word level? • Bit level vs word level in *BMDs - example 4 4 2 2 1 1 M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

  18. Bit level representation of addition • Derived using gate level representation of the circuit • Sum using XORs and carry using AND, OR gates Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

  19. 0 1 y0 y1 y2 x0 x1 x2 Representation of word level operations - Product • Product X*Y • Both X and Y here are 3 bit wide • X= 4x2+2x1+x0 Y= 4y2+2y1+y0 • X*Y = (4x2+2x1+x0)*(4y2+2y1+y0) = 4x2*(4y2+2y1+y0) + 2x1 *(4y2+2y1+y0) + x0*(4y2+2y1+y0) • Variable order x2x1x0y2y1y0 • Linear with n- #bits 4 2 1 4 2 1 M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification.

  20. Verification Problem • Goal: To prove equivalence between the bit level circuit and word level specification • Circuit output interpreted as word should match the specification when applied to word level interpretations of the input Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

  21. Hierarchical verification using *BMDs • *BMDs can represent both bit level and word level functions efficiently • Circuit partitioned into component modules based on word level structures • Each component verified against the word level specification • Word level functions are composed and compared to overall circuit specification • Addition • Compute P using the bitwise *BMD results • Compare the *BMD for P with the word level representation of X+Y

  22. Hierarchical verification using *BMDs • Multiplication • Circuits like multipliers cannot be verified efficiently at bit level (why?) Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

  23. Hierarchical verification using *BMDs • Each box (i,j) represents a cell containing an AND gate to form the partial product and a Full Adder (FA) to add this bit to the product • Vertical rectangles indicate the word level partitioning of the circuit • Add Stepi has • input multiplicand word X • One bit multiplier yi • Partial sum input word Pi • Generates a output word Po using • Verification involves • Checking each component • Composition of word level functions matching integer multiplication

  24. Results • Number of multiplier circuits with different word sizes are used (16 bit, 64 bit and 256 bit) • Metrics – CPU minutes and memory • Maximum 33 min on 256 bit word and 14.4 MB of memory • Can verify circuits with upto 256 bit word sizes requiring 653,056 logic gates • Ochi et. al verified successfully 15 bit word size using 12 million vertices • Increasing one bit increases number of vertices by 2.7 • Jain et al used Indexed BDDs to verify multipliers • It took almost 4 hours of CPU time Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995

  25. Summary • *BMDs for mapping Boolean variables to numeric values • Construction of *BMDs • reduction rules • Normalization • Representing Boolean logic • Word level • Hierarchical verification • Component verification • Word level comparison

  26. References • [1] Bryant,R.E and Chen Y-A. “Verification of arithmetic circuits with binary moment diagrams”, DAC 1995 • [2] M Ciesielski, D K Pradhan and A M Jabir, “Decision diagrams for verification”, chapter-7, Practical Design Verification

  27. Thank You!

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