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Design and System Driver Chapters July Meeting San Francisco, California Design TWG (Europe, Japan, and U.S.)

Design and System Driver Chapters July Meeting San Francisco, California Design TWG (Europe, Japan, and U.S.).

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Design and System Driver Chapters July Meeting San Francisco, California Design TWG (Europe, Japan, and U.S.)

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  1. Design and System Driver ChaptersJuly Meeting San Francisco, CaliforniaDesign TWG (Europe, Japan, and U.S.) Albin, Arledge, Asada,Bernstein, Bertacco, Blaauw, Blanton,Brederlow,Briere,Carballo, Chen,Cohn,Cottrell,Darringer,Edwards,Furui,Gowda, Grimm, Grimpe, Guardiani, Haggag, Hiwatashi, Kahng, Kashiwagi,Kawahira,Kozawa,Ishibashi,Joyner, Kahng, Kim, Kravets, Malhotra, Macd, Malhotra,Margala, Martin, McMillan, Meixner, Nassif, Ozev, Pan, Nukiyama, Pan, Pitchumani, Pixley,Redmond, Rosenstiel, Read, Rodgers, Sakallah, Smith,Soma,Stok,Schwarz, Vertregt,Vörg, Wilson, Wong, Yamamoto, Yamada, Yeh,

  2. What’s New in 2005 Design & System Drivers • First Design For Manufacturability roadmap DFM roadmap tool Interface with other groups • First worldwide quantitative design technology roadmap System-level Logic/circuit/layout Verification DFT DFM • New SoC model captures emerging market driver Consumer driver improves alignment with other roadmaps • Emerging SoC fabric drivers updated Analog & MIxed-signal Embedded memory In next 10 years, new drivers and technology limitations will require design technology overhaul at all abstraction levels

  3. Design: Content organization • Promotion of key design challenges • Small subset of them as top-level ORTC table General Selection Productivity Power DFM Interference Reliability Mapping Design process System design Logic/circuit Physical D Design verification Design Test DFM (new)

  4. New:Overall Design Technology Challenges

  5. New:Overall Design Technology Challenges

  6. Design Technology Cycle (Pre-Production) ~10-year cycle

  7. Design Technology Cycle (Production) ~10-year cycle

  8. 1. Design Technology Roadmap (tables)

  9. 1. Detailed Tables/SectionsTopics and Leads • System level design • Wolfgang Rosenstiel (University of Tuebingen) • Logic/circuit/physical design • Victor Kravets (IBM) • Verification • Valeria Bertacco (University of Michigan) • Test • Mani Soma (University of Washington) • DFM • Sani Nassif (IBM), Carballo/Kahng (IBM/UCSD) • Mobile consumer system driver • Japan/STRJ

  10. Detailed Table Status • Drafts under review • Targeting ~100 new rows, ~10 per table • Currently 49 solutions, 43 requirements

  11. Revised System-Level Requirements Source: Wolfgang Rosenstiel’s Team

  12. Logic/Circuit/Physical Solutions

  13. Revised DFT Solutions Table

  14. 2. Design For Manufacturability Roadmap

  15. DFM  Variability Framework Actual (bottom-up) / required (top-down) variability Performance (delay) Power (energy) “Gate” delay (power) “Wire” delay (power) Intermediate parameters Intermediate parameters (Vdd, T) Rsheet Vt Leff tOX NA Weff L t W tILD Other TWGs (PIDS, Interconnect, etc.)

  16. Roadmapping DFM Issues inc. Variability • Current recommendation • Not to extend 10% CD control beyond 15% • Below 15% still unclear  12% possibly acceptable

  17. 3. New System-On-Chip Driver

  18. 4. System Drivers “Matrix” Alignment Fabrics HP CP MPU PE(DSP) Size/weight ratio, battery life… Power, interconnect speed… Memory Markets AMS Medical Automotive Office Network Defense Portable [Industrial]

  19. 2. SoC Cost Model Update, Inc. SW(Japan Design TWG) ES Level Methodology Very large block reuse Intelligent testbench Large block reuse Small block reuse Tall thin engineer IC implem. tools In-house P&R General $10,000 $1,000 Selection Productivity Power Manufac. Interference Reliability $100 Design cost ($M) $10 $1 Design process System design Logic/circuit Physical D Design verification Design Test DFM (new) 1990 1996 2000 2002 2004 2010 1992 1994 1998 2006 2008 Mobile /Consumer SoC PE-1 PE-2 … PE-n Main Prc. Memory Updated productivity table  cost Peripherals Preserve consistency

  20. Key Driver Trends • Power consumption a first-class constraint Both for portable and non-portable applications • Highly parallel architectures Increasing number of “small” processing unit • System-On-Chip design techniques Assemble lots of pre-designed blocks

  21. --- Overall Requirements (cont.) SOC Requirements

  22. --- Design Complexity Trends (cont.) SOC Complexity Trends

  23. --- Power Trends (cont.) SOC Power Trends

  24. --- Processing Performance Trends (cont.) SOC Processing Performance Trends

  25. What’s New in 2005 Design & System Drivers • First Design For Manufacturability roadmap DFM roadmap tool Interface with other groups • First worldwide quantified design technology roadmap System-level Logic/circuit/layout Verification DFT DFM • New SoC model captures emerging market driver Consumer driver improves alignment with other roadmaps • Emerging SoC fabric drivers updated Analog & MIxed-signal Embedded memory In next 10 years, new drivers and technology limitations will require design technology overhaul at all abstraction levels

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