EE365 Adv. Digital Circuit Design Clarkson University Lecture #13 Clock Skew & Synchronization

1. EE365 Adv. Digital Circuit Design Clarkson University Lecture #13 Clock Skew & Synchronization

2. Topics • More Serial • Clock Skew • Synchronization Lect #13 Rissacher EE365

3. Serial data systems (e.g., TPC) Lect #13 Rissacher EE365

4. Serial data in the phone system (E-1) • 2.048 Mb/s links between phone switches and subscribers • partitioned into 32 64 Kb/s channels • Each channel gets a timeslot in a “frame” where it can send 8 bits every 125 sec. • 8000 frames/sec Lect #13 Rissacher EE365

5. count = 255 Timeslot details Lect #13 Rissacher EE365

6. 256 LSBs are bit number Assert shift-registerLOAD input during bit 7 Timeslot number canbe decoded and usedto select source ofparallel data count = 255 Serial data todestination Parallel-to-serial conversion Lect #13 Rissacher EE365

7. Synchronize destination’s counter to source’s Detect that acomplete bytehas beenreceived Note: loads 0…0 Holding registerfor completebyte Shift in serial data Serial-to-parallel conversion Lect #13 Rissacher EE365

8. Grab complete byte when available Holding-register outputs Serial-in, parallel-outshift register outputs Destination timing Lect #13 Rissacher EE365

9. Serial communication on ONE wire • Serial communication requires three signals: CLOCK, SYNC, and DATA. Yet only one “wire” is used. How? • One solution: Manchester code. • Or use a phase-locked loop (analog circuit)to extract clock from the data: Lect #13 Rissacher EE365

10. Still a couple of problems • Framing -- SYNC signal • Solution: Use a unique data pattern for SYNC • PLL clock recovery -- what if too many zeroes are transmitted? PLL can’t stay in sync. • Solution: Use a code that guarantees a minimum number of ones • Phone system: Map 00000000 --> 00000010 (creating slight voice distortion) • Gigabit Ethernet: Uses 8B10B code, solving both problems • Map each byte into 8 bits • Use only a “good” subset of 210 code words • Use another code word for synchronization Lect #13 Rissacher EE365

11. Synchronous System Structure Everything is clocked by the same, common clock Lect #13 Rissacher EE365

12. Typical synchronous-system timing • Outputs have one complete clock period to propagate to inputs. • Must take into account flip-flop setup times at next clock period. Lect #13 Rissacher EE365

13. Clock Skew • Clock signal may not reach all flip-flops simultaneously. • Output changes of flip-flops receiving “early” clock may reach D inputs of flip-flops with “late” clock too soon. Reasons for slowness:(a) wiring delays (b) capacitance (c) incorrect design Lect #13 Rissacher EE365

14. Clock-skew calculation • tffpd(min) + tcomb(min)-thold-tskew(max) > 0 • First two terms are minimum time after clock edge that a D input changes • Hold time is earliest time that the input may change • Clock skew subtracts from the available hold-time margin • Compensating for clock skew: • Longer flip-flop propagation delay • Explicit combinational delays • Shorter (even negative) flip-flop hold times Lect #13 Rissacher EE365

15. In-Class Practice Problem Calculate whether clock-skew is an issue for the indicated Flip-Flop Comb Logic (Excitation Eqns) tffpd(min) = 5 ns tcomb(min) = 20 ns thold = 20 ns tskew(max) = 10 ns CLK Delay Lect #13 Rissacher EE365

16. In-Class Practice Problem Calculate whether clock-skew is an issue for the indicated Flip-Flop tffpd(min) = 5 ns tcomb(min) = 20 ns thold = 20 ns tskew(max) = 10 ns tffpd(min) + tcomb(min)-thold-tskew(max) = -5 ns Lect #13 Rissacher EE365

17. In-Class Practice Problem Now add a delay to the circuit to fix the issue. Comb Logic (Excitation Eqns) tffpd(min) = 5 ns tcomb(min) = 20 ns thold = 20 ns tskew(max) = 10 ns CLK Delay Lect #13 Rissacher EE365

18. In-Class Practice Problem > 5 ns Comb Logic (Excitation Eqns) tffpd(min) = 5 ns tcomb(min) = 20 ns thold = 20 ns tskew(max) = 10 ns CLK Delay Lect #13 Rissacher EE365

19. Example of bad clock distribution Lect #13 Rissacher EE365

20. Clock distribution in ASICs • This is what a typical ASIC router will do if you don’t lay out the clock by hand. Lect #13 Rissacher EE365

21. “Clock-tree” solution • Often laid out by hand • Wide,fast metal (low R ==> fast RC time constant) Lect #13 Rissacher EE365

22. Gating the clock • Definitely a no-no • Glitches possible if control signal (CLKEN) is generated by the same clock • Excessive clock skew in any case. Lect #13 Rissacher EE365

23. If you really must gate the clock... Lect #13 Rissacher EE365

24. Asynchronous inputs • Not all inputs are synchronized with the clock • Examples: • Keystrokes • Sensor inputs • Data received from a network (transmitter has its own clock) • Inputs must be synchronized with the system clock before being applied to a synchronous system. Lect #13 Rissacher EE365

25. A simple synchronizer Lect #13 Rissacher EE365

26. Only one synchronizer per input Lect #13 Rissacher EE365

27. Even worse • Combinational delays to the two synchronizers are likely to be different. Lect #13 Rissacher EE365

28. The way to do it • One synchronizer per input • Carefully locate the synchronization points in a system. • But still a problem -- the synchronizer output may become metastable when setup and hold time are not met. Lect #13 Rissacher EE365

29. Recommended synchronizer design • Hope that FF1 settles down before “META” is sampled. • In this case, “SYNCIN” is valid for almost a full clock period. • Can calculate the probability of “synchronizer failure” (FF1 still metastable when META sampled) Lect #13 Rissacher EE365

30. Metastability decision window Lect #13 Rissacher EE365

31. Metastability resolution time Lect #13 Rissacher EE365

32. Flip-flop metastable behavior • Probability of flip-flop output being in the metastable state is an exponentially decreasing function of tr (time since clock edge, a.k.a. “resolution time”). • Stated another way,MTBF(tr) = exp(tr /t) / [T0fa] , wheret and T0 are parameters for a particular flip-flop,f is the clock frequency, anda is the number of asynchronous transitions / sec Lect #13 Rissacher EE365

33. MTBF = exp(tr /t) ________ [T0fa] Typical flip-flop metastability parameters MTBF = 1000 yrs. F = 25 MHz a = 100 KHz tr = ? Lect #13 Rissacher EE365

34. Is 1000 years enough? • If MTBF = 1000 years and you ship 52,000 copies of the product, then some system experiences a mysterious failure every week. • Real-world MTBFs must be much higher. • How to get better MTBFs? • Use faster flip-flops • But clock speeds keep getting faster, thwarting this approach. • Wait for multiple clock ticks to get a longer metastabilty resolution time • Waiting longer usually doesn’t hurt performance • …unless there is a critical “round-trip” handshake. Lect #13 Rissacher EE365

35. Multiple-cycle synchronizer • Clock-skew problem Lect #13 Rissacher EE365

36. De-skewed multiple-cycle synchronizer • Necessary in really high-speed systems • DSYNCIN is valid for almost an entire clock period. Lect #13 Rissacher EE365

37. Next time • CPLDs • FPGAs Lect #13 Rissacher EE365