EE365 Adv. Digital Circuit Design Clarkson University Lecture #14 SRAM & DRAM

1. EE365 Adv. Digital Circuit Design Clarkson University Lecture #14 SRAM & DRAM

2. Topics • SRAM • DRAM Lect #15 Rissacher EE365

3. Read/Write Memories • a.k.a. “RAM” (Random Access Memory) • Volatility • Most RAMs lose their memory when power is removed • NVRAM = RAM + battery • Or use EEPROM • SRAM (Static RAM) • Memory behaves like latches or flip-flops • DRAM (Dynamic Memory) • Memory lasts only for a few milliseconds • Must “refresh” locations by reading or writing Lect #15 Rissacher EE365

4. SRAM Lect #15 Rissacher EE365

5. SRAM operation • Individual bits are D latches, notedge-triggered D flip-flops. • Fewer transistors per cell. • Implications for write operations: • Address must be stable before writing cell. • Data must be stable before ending a write. Lect #15 Rissacher EE365

6. SRAM array Lect #15 Rissacher EE365

7. SRAM control lines • Chip select • Output enable • Write enable Lect #15 Rissacher EE365

8. SRAM read timing • Similar to ROM read timing Lect #15 Rissacher EE365

9. SRAM write timing • Address must be stable before and after write-enable is asserted. • Data is latched on trailing edge of (WE & CS). Lect #15 Rissacher EE365

10. Bidirectional data in and out pins • Use the same data pins for reads and writes • Especially common on wide devices • Makes sense when used with microprocessor buses (also bidirectional) Lect #15 Rissacher EE365

11. SRAM devices • Similar to ROM packages 28-pin DIPs 32-pin DIPs Lect #15 Rissacher EE365

12. Synchronous SRAMs • Use latch-type SRAM cells internally • Put registers in front of address and control (and maybe data) for easier interfacing with synchronous systems at high speeds • E.g., Pentium cache RAMs Lect #15 Rissacher EE365

13. DRAM (Dynamic RAMs) • SRAMs typically use six transistors per bit of storage. • DRAMs use only onetransistor per bit: • 1/0 = capacitorcharged/discharged Lect #15 Rissacher EE365

14. DRAM read operations • Precharge bit line to VDD/2. • Take the word line HIGH. • Detect whether current flows into or out of the cell. • Note: cell contents are destroyed by the read! • Must write the bit value back after reading. Lect #15 Rissacher EE365

15. DRAM write operations • Take the word line HIGH. • Set the bit line LOW or HIGH to store 0 or 1. • Take the word line LOW. • Note: The stored charge for a 1 will eventually leak off. Lect #15 Rissacher EE365

16. DRAM charge leakage • Typical devices require each cell to be refreshed once every 4 to 64 mS. • During “suspended” operation, notebook computers use power mainly for DRAM refresh. Lect #15 Rissacher EE365

17. DRAM-chip internal organization 64K x 1DRAM Lect #15 Rissacher EE365

18. RAS/CAS operation • Row Address Strobe, Column Address Strobe • n address bits are provided in two steps using n/2 pins, referenced to the falling edges of RAS_L and CAS_L • Traditional method of DRAM operation for 20 years. • Now being supplanted by synchronous, clocked interfaces in SDRAM (synchronous DRAM). Lect #15 Rissacher EE365

19. DRAM read timing Lect #15 Rissacher EE365

20. DRAM refresh timing Lect #15 Rissacher EE365

21. DRAM write timing Lect #15 Rissacher EE365

22. Next time • There is no next time • Next Class: I’ll be here to answer any exam questions Lect #15 Rissacher EE365