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EE365 Adv. Digital Circuit Design Clarkson University

EE365 Adv. Digital Circuit Design Clarkson University. HW#4 Help. Be aware of proper Bit order A  A ? Not Necessarily MSB  MSB LSB  LSB. Rissacher EE365. HW#4 Help. Device. Circuit Description. Rissacher EE365. HW#4 Help. MSB. Rissacher EE365. More VHDL.

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EE365 Adv. Digital Circuit Design Clarkson University

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  1. EE365 Adv. Digital Circuit Design Clarkson University

  2. HW#4 Help • Be aware of proper Bit order • A  A ? Not Necessarily • MSB  MSB • LSB  LSB Rissacher EE365

  3. HW#4 Help Device Circuit Description Rissacher EE365

  4. HW#4 Help MSB Rissacher EE365

  5. More VHDL • Projects will get more complex (devices and circuits will be more difficult to define) • In Proj #3, don’t worry about “minimization” of circuit, just make it work with MSI devices… there may be more than one way to create a successful device • However, complexity of your design will be considered in the grade (overly large circuits will lose some points) • May need to learn some more VHDL syntax

  6. VHDL: Concatenation Given several bits (e.g., A0, A1, A2), they can be concatenated using the ‘&’ operator For example: A0 = ‘1’ A1 = ‘0’ A2 = ‘0’ (A0 & A1 & A2) = ‘100’

  7. VHDL: Concatenation Concatenated terms can be used for relational operations For example: F <= ‘1’ after 20ns when (A0 & A1 & A2) = ‘100’ …

  8. VHDL: More Complex Devices • MSI devices are more complex and will be harder to define. • The may have several inputs and several outputs • For each output, use a separate concurrent statement • For example: • F <= ‘1’ after 20ns when (A0 & A1 & A2) = ‘100’ else ‘0’ after 20 ns; • G <= ‘1’ after 40ns when (A0 & A1 & A2) > ‘000’ else ‘0’ after 40 ns;

  9. VHDL: More Complex Devices • May need very long statements to define all of the possibilities that drive a certain output • For example: • F <= ‘1’ after 20 ns when (A=‘1’) or (B=‘1’) or (C=‘1’) or ((D=‘1’)and(EN_L=‘0’)) or (BYP_L = ‘0’) else ‘0’ after 60 ns; • (And they can get much worse)

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