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EE365 Adv. Digital Circuit Design Clarkson University Lecture #8

EE365 Adv. Digital Circuit Design Clarkson University Lecture #8 Buffers, Drivers, Encoders, MUXs & XORs. Topics. Buffers Drivers Encoders Multiplexers Exclusive OR Gates. Lect #8. Rissacher EE365. Three-state buffers. Output = LOW, HIGH, or Hi-Z.

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EE365 Adv. Digital Circuit Design Clarkson University Lecture #8

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  1. EE365 Adv. Digital Circuit Design Clarkson University Lecture #8 Buffers, Drivers, Encoders, MUXs & XORs

  2. Topics • Buffers • Drivers • Encoders • Multiplexers • Exclusive OR Gates Lect #8 Rissacher EE365

  3. Three-state buffers • Output = LOW, HIGH, or Hi-Z. • Can tie multiple outputs together, if at most one at a time is driven. Lect #8 Rissacher EE365

  4. Different flavors Lect #8 Rissacher EE365

  5. Lect #8 Rissacher EE365

  6. Timing considerations Lect #8 Rissacher EE365

  7. Three-state drivers Lect #8 Rissacher EE365

  8. Driver application Lect #8 Rissacher EE365

  9. Three-state transceiver Lect #8 Rissacher EE365

  10. Transceiver application Lect #8 Rissacher EE365

  11. Decoder Encoder Encoders vs. Decoders Lect #8 Rissacher EE365

  12. Binary encoders Lect #8 Rissacher EE365

  13. Need priority in most applications Lect #8 Rissacher EE365

  14. 8-input priority encoder Lect #8 Rissacher EE365

  15. Priority-encoder logic equations Lect #8 Rissacher EE365

  16. 74x148 8-input priority encoder • Active-low I/O • Enable Input • “Got Something” • Enable Output Lect #8 Rissacher EE365

  17. 74x148circuit Lect #8 Rissacher EE365

  18. 74x148 Truth Table Lect #8 Rissacher EE365

  19. In Class Practice Problem Write the truth table for a 4-to-2 encoder: • No enables • Active High inputs and outputs Lect #8 Rissacher EE365

  20. In Class Practice Problem Lect #8 Rissacher EE365

  21. Cascading priority encoders • 32-inputpriority encoder Lect #8 Rissacher EE365

  22. Constant expressions Lect #8 Rissacher EE365

  23. Outputs Lect #8 Rissacher EE365

  24. Alternative formulation • WHEN is very natural for priority function Lect #8 Rissacher EE365

  25. Multiplexers Lect #8 Rissacher EE365

  26. 74x1518-input multiplexer Lect #8 Rissacher EE365

  27. 74x151 truth table Lect #8 Rissacher EE365

  28. CMOS transmission gates • 2-input multiplexer Lect #8 Rissacher EE365

  29. Other multiplexer varieties • 2-input, 4-bit-wide • 74x157 • 4-input, 2-bit-wide • 74x153 Lect #8 Rissacher EE365

  30. In Class Practice Problem Write the truth table for a 1-to-4 line Multiplexer: • No enables • Active High inputs and outputs Lect #8 Rissacher EE365

  31. In Class Practice Problem Lect #8 Rissacher EE365

  32. Barrel shifter design example • n data inputs, n data outputs • Control inputs specify number of positions to rotate or shift data inputs • Example: n = 16 • DIN[15:0], DOUT[15:0], S[3:0] (shift amount) • Many possible solutions, all based on multiplexers Lect #8 Rissacher EE365

  33. 16 16-to-1 MUXs 16-to-1 mux = 2 x 74x151 8-to-1 mux + NAND gate Lect #8 Rissacher EE365

  34. 4 16-bit 2-to-1 MUXs 16-bit 2-to-1 mux = 4 x 74x157 4-bit 2-to-1 mux Lect #8 Rissacher EE365

  35. Properties of different approaches Lect #8 Rissacher EE365

  36. 2-input XOR gates • Like an OR gate, but excludes the case where both inputs are 1. • XNOR: complement of XOR Lect #8 Rissacher EE365

  37. XOR and XNOR symbols Lect #8 Rissacher EE365

  38. Gate-level XOR circuits • No direct realization with just a few transistors. Lect #8 Rissacher EE365

  39. CMOS XOR with transmission gates IF B==1 THEN Z = !A; ELSE Z = A; Lect #8 Rissacher EE365

  40. Multi-input XOR • Sum modulo 2 • Parity computation • Used to generate and check parity bits in computer systems. • Detects any single-bit error Lect #8 Rissacher EE365

  41. Parity tree • Faster with balanced tree structure Lect #8 Rissacher EE365

  42. Next time • Comparators • Adders • Multipliers • Read-only memories (ROMs) Lect #8 Rissacher EE365

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