480 likes | 645 Views
EE365 Adv. Digital Circuit Design Clarkson University Lecture #5 Electrical Behavior of Logic Circuits. Topics. Electrical Characteristics Noise & Noise Margins Voltage Levels Fan-in Fan-out Output Types Timing Characteristics Transition Delay. Lect #5. Rissacher EE365.
E N D
EE365 Adv. Digital Circuit Design Clarkson University Lecture #5 Electrical Behavior of Logic Circuits
Topics • Electrical Characteristics • Noise & Noise Margins • Voltage Levels • Fan-in • Fan-out • Output Types • Timing Characteristics • Transition Delay Lect #5 Rissacher EE365
Logic levels • Undefined regionis inherent • digital, not analog • Switching threshold varies with voltage, temp, process, phase of the moon • need “noise margin” • The more you push the technology, the more “analog” it becomes. • Logic voltage levels decreasing with process • 5 -> 3.3 -> 2.5 -> 1.8 V Lect #5 Rissacher EE365
Electrical Characteristics • Digital analysis works only if circuits are operated in spec: • Power supply voltage • Temperature • Input-signal quality • Output loading • Must do some “analog” analysis to prove that circuits are operated in spec. Lect #5 Rissacher EE365
Output Specifications • Voltage: • VOLmax and VOHmin • Current: • Output sinks current when current flows into the output - max low state output current: IOLmax • Output sources current when current flow out of the output - max high state output current: IOHmax Lect #5 Rissacher EE365
DC Loading • An output must source current to a load when the output is in the HIGH state. • An output must sink current from a load when the output is in the LOW state. Lect #5 Rissacher EE365
Output-voltage drops • Resistance of “off” transistor is > 1 Megohm, but resistance of “on” transistor is nonzero, • Voltage drops across “on” transistor, V = IR • For “CMOS” loads, current and voltage drop are negligible. • For TTL inputs, LEDs, terminations, or other resistive loads, current and voltage drop are significant and must be calculated. Lect #5 Rissacher EE365
Output-drive specs • VOLmax and VOHmin are specified for certain output-current values, IOLmax and IOHmax • No need to know details about the output circuit, only the load. • CMOS devices typically have two sets of output drive specs: • CMOS loads • TTL or other resistive loads Lect #5 Rissacher EE365
Manufacturer’s data sheet Lect #5 Rissacher EE365
Driving Non-Ideals Loads • Many typical loads may be represented by a resistive network • Find the Thevenin equivalent circuit (review from ES 250) of the load • Compute the output current and voltages to determine if they are within specification Lect #5 Rissacher EE365
Example loading calculation • Need to know “on” and “off” resistances of output transistors, and know the characteristics of the load. Lect #5 Rissacher EE365
Estimating Values for Internal Resistances • Estimate the value of the internal resistances from the specification for maximum output current. • Effective p-channel on resistance is Rp = [ VDD - VOHmin ] / | IOHmax | • Effective n-channel on resistance is Rn = VOLmax / IOLmax Lect #5 Rissacher EE365
Example Using Estimated Values => Output Specifications for CMOS (HC) driving TTL loads VOHmin = 4.3 v VOLmax = 0.33 v IOHmax = - 4.0 ma IOLmax = 4.0 ma Rp = [5 - 4.3] v / 4 ma = 175. ohms Rn = 0.33 v / 4 ma = 82.5 ohms High State: Iout = - [5 - 3.3] / [175 + 667] = - 2 ma Vout = 5 - ( 0.002 x 175) = 4.65 v High State Model Lect #5 Rissacher EE365
Limitation on DC load • If too much load, output voltage will go outside of valid logic-voltage range. • VOHmin, VIHmin • VOLmax, VILmax Lect #5 Rissacher EE365
Input-loading specs • Each gate input requires a certain amount of current to drive it in the LOW state and in the HIGH state. • IIL and IIH • These amounts are specified by the manufacturer. Lect #5 Rissacher EE365
Fan-out The fan-out of a logic gate is the number of inputs that the gate can drive without exceeding its worst-case loading specs. 1 Fan-out N Lect #5 Rissacher EE365
Computing Fan-out • General fan-out is the minimum of • high state fan-out • low state fan-out • In each case, determine max input current of each expected load and max output current of the driving device • Fan-out = max outputDEVICE / max inputLOAD • Fan-outL = IOLmax/IILmax (for high state L H) Lect #5 Rissacher EE365
In-Class Practice Problem • Find the fan-out of the following device when connected to identical devices Lect #5 Rissacher EE365
In-Class Practice Problem • Find the fan-out of the following device when connected to identical devices -20 μA / ±1.0 μA = 20 (minimum of two states) Lect #5 Rissacher EE365
Fan-out Note • Generally, when driving CMOS devices, fanout is nearly unlimited because CMOS inputs require almost no current • When driving TTL devices, this is not the case Lect #5 Rissacher EE365
Fan-in For a given logic family, the maximum number of inputs available on any one gate is called the fan-in. 1 Fan-in N Lect #5 Rissacher EE365
Fan-in • Limited in practice by the characteristics of a particular technology. • For CMOS, limited by the additive “on” resistance of series transistors in either the PUN or PDN. • Typical values are 4 for NOR gates and 6 for NAND gates. • No need to calculate Lect #5 Rissacher EE365
Fan-in • Cascade Structure for Large Inputs works around the fan-in limitation • 8-input CMOS NAND: Lect #4 Lect #5 Rissacher EE365 Rissacher EE365
Non-Ideal Inputs • What happens if the gate input is not nearly zero or nearly +5 v ? • Can occur if driven by devices of another logic family (e.g. TTL drives CMOS) • Inputs may still meet VIHmin or VILmax Lect #5 Rissacher EE365
Non-Ideal Inputs Output High State If Vin = 0 v. => p-channel device conducts n-channel device is off As Vin increases n-channel device begins to turn-on Output Low State If Vin = 5 v => p-channel device is off n-channel device conducts As Vin decreases p-channel device begins to turn-on Lect #5 Rissacher EE365
Non-Ideal Inputs • Example: suppose input voltage is ~ 1.3 v instead of 0 v. • The p-transistors will have increased resistance • The n-transistors will have decreased resistance • Result: output voltage will be reduced, but still above VOHmin • Also increased current flow from VDD to ground • Result: increased power consumption Lect #5 Rissacher EE365
Unused Inputs • A three NAND is available, but you only need a two input NAND - what about the unused input? • Logically, an unused input should be: • a constant logic 1 for a NAND gate • a constant logic 0 for a NOR gate • identical to any one of the other inputs Lect #5 Rissacher EE365
Unused Inputs Lect #5 Rissacher EE365
Unused Inputs - CMOS • Electrically, must NOT be left unconnected • Very high input impedance => any noise can cause the apparent input value to change between a logic 0 and a logic 1. • Highly susceptible to electrostatic discharge (ESD) • Loose devices easily destroyed on a winter’s day in Potsdam ! Lect #5 Rissacher EE365
Unused Inputs - TTL • May be left “open” (appears as logic 1) • Can be changed by noise • If pulled high or low by resistor, must carefully compute resistor value since input current not negligible Lect #5 Rissacher EE365
Dynamics • Fanout also limited by dynamic considerations • Switching from low to high state or high to low cannot happen instantly - why not ? • If the load has any capacitive effects, what do you know about voltage across a capacitor? Lect #5 Rissacher EE365
+ 5 v 0 v Dynamics Vout = VDD e -t/ Rn C Lect #5 Rissacher EE365
AC Loading • AC loading has become a critical design factor as industry has moved to pure CMOS systems. • CMOS inputs have very high impedance, DC loading is negligible. • CMOS inputs and related packaging and wiring have significant capacitance. • Time to charge and discharge capacitance is a major component of delay. Lect #5 Rissacher EE365
Transition times Lect #5 Rissacher EE365
Circuit for transition-time analysis Lect #5 Rissacher EE365
HIGH-to-LOW transition Lect #5 Rissacher EE365
Exponential rise time Lect #5 Rissacher EE365
LOW-to-HIGH transition Lect #5 Rissacher EE365
Exponential fall time t = RC time constant exponential formulas, e-t/RC Lect #5 Rissacher EE365
Transition-time considerations • Higher capacitance ==> more delay • Higher on-resistance ==> more delay • Lower on-resistance requires bigger transistors • Slower transition times ==> more power dissipation (output stage partially shorted) • Faster transition times ==> worse transmission-line effects (Chapter 11) • Higher capacitance ==> more power dissipation (CV2f power), regardless of rise and fall time Lect #5 Rissacher EE365
Open-drain outputs • No PMOS transistor, use resistor pull-up Lect #5 Rissacher EE365
Open-drain transition times • Pull-up resistance is larger than a PMOS transistor’s “on” resistance. • Can reduce rise time by reducing pull-up resistor value • But not too much Lect #5 Rissacher EE365
Power Consumption • Static power dissipation - no signal transitions • Dynamic power dissipation - signal transitions • P = [ CPD + CL ] VDD2 f , where f is the frequency of signal transitions Lect #5 Rissacher EE365
TTL (S, LS, AL, ALS, F) 5 v 0 v Comparison of Signal Levels CMOS (HC, AC) CMOS (HCT, ACT) 5 v 5 v VOH 4.4 v VIH 3.5 v VOH 2.4 v VOH 2.4 v VIH VIH 2.0 v 2.0 v VIL 1.5 v 0.8 v 0.8 v VIL VIL 0.5 v 0.4 v VOL 0.4 v VOL VOL 0 v 0 v Lect #5 Rissacher EE365
TTL Input Specifications • Unlike CMOS, TTL gates sink or source current at the input • Fanout must examine input currents and output currents • Low state input sources current ( it flows out of the device) • High state input sinks current • LS-TTL: IILmax= -0.4 mA; IIHmax= 20 A Lect #5 Rissacher EE365
TTL Output Specifications • Similar to CMOS • LS-TTL: IOLmax = 8 mA; IOHmax = -400 A • High state fanout = low state fanout = 20 • But note that TTL has very asymmetric output drive capability • low state output can sink much more than high state output • moderate current loads only in low state Lect #5 Rissacher EE365
TTL differences from CMOS • Asymmetric input and output characteristics. • Inputs source significant current in the LOW state, leakage current in the HIGH state. • Output can handle much more current in the LOW state (saturated transistor). • Output can source only limited current in the HIGH state (resistor plus partially-on transistor). • TTL has difficulty driving “pure” CMOS inputs because VOH = 2.4 V (except “T” CMOS). Lect #5 Rissacher EE365
Next Class • Timing Considerations • Propagation Delay • Hazards Lect #5 Rissacher EE365