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Highlights of 2004 updates and plans for 2005 updates to the Lithography chapter of the ITRS

Highlights of 2004 updates and plans for 2005 updates to the Lithography chapter of the ITRS. Lithography International Technical Working Group April, 2005. Lithography ITWG Chair persons and Co-chair persons for 2004 and 2005. Summary of 2004 Lithography Chapter Updates.

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Highlights of 2004 updates and plans for 2005 updates to the Lithography chapter of the ITRS

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  1. Highlights of 2004 updates and plans for 2005 updates to the Lithography chapter of the ITRS Lithography International Technical Working Group April, 2005

  2. Lithography ITWG Chair persons and Co-chair persons for 2004 and 2005

  3. Summary of 2004 Lithography Chapter Updates • Defined more specific criteria for evaluating near-term potential solutions • Stronger emphasis on difficult challenges related to immersion lithography • Continued emphasis on challenges for implementing cost-effective post-optical lithography solutions

  4. Changes to Lithography Table Values in 2004 • CD control (total CD control) • US and Japan TWG studies concluded that <4nm 3s CD control has no known solutions • CD control will remain red for the present and future nodes • Printed gate length in resist values will be re-evaluated in 2005 • Changes to coloring, footnotes, etc. • Definition of overlay in overall lithography requirements Tables 77a and 77b • Mask table values updated • Resist table values updated

  5. More specific criteria for potential solutions • All infrastructure (masks, tools, resist,…) needs to be in place to meet the ramp for the specified node • Technology must be planned to be used by IC makers in at least two geographical regions • For N+3 and later nodes with black coloring, the requirement to have more than one region support is not applicable • Technology should be targeting leading edge critical layer needs • Consideration (not a requirement): 100 tools worldwide over the life of that tool generation

  6. 2010 2019 2004 2007 2016 2013 Technology Node hp90 hp65 hp45 hp32 hp22 hp16 Technology Options at Technology Nodes(DRAM Half-Pitch, nm) 90 193 nm DRAM Half-pitch(dense lines) 193nm + LFD 193nm immersion PEL RET = Resolution enhancement technology LFD = Lithography friendly design rules ML2 = Maskless lithography 65 193nm immersion + LFD EUV ML2, 157nm immersion, PEL 45 EUV 193nm immersion + LFD 157nm immersion + LFD, ML2 Imprint 32 EUV Innovative 157nm or 193 nm immersion ML2 Imprint, innovative technology 22 Innovative technology ML2, EUV + RET, imprint 16 Research Required Development Underway Qualification/Pre-Production Continuous Improvement Lithography Potential Solutions in 2004 Update 2004 Lithography exposure tool potential solutions Unofficial version of Figure 34; Not for publication Notes: EPL is a potential solution at the 65, 45 and 32-nm nodes for one geographical region, and PEL is a potential solution at the 32-nm node for one geographical region. RET will be used with all optical lithography solutions, including with immersion; therefore, it is not explicitly noted.

  7. KrF+PSM 2003 Edition 140 2004 Update 130@2001 120 ArF+PSM 100 90 90@2004 80 F2+PSM 70 IPL PXL PEL 65@2007 60 PEL ArF+RET+LFD+Immersion 50 ArF +LFD+Immersion PEL 45@2010 F2+ LFD+Immersion F2+RET+LFD+Immersion 40 EPL EPL EUV ML2 EUV EUV EPL ML2 ML2 32@2013 PEL Imprint 30 Imprint 22@2016 Innovative Immersion +RET 20 Innovation Innovation Innovation +RET History of ITRS Litho Potential Solutions 2001 Edition Source: Kameyama, Nikon

  8. Difficult Challenges - Short Term (1)

  9. Difficult Challenges - Short Term (2)

  10. Difficult Challenges - Long Term (1)

  11. Difficult Challenges - Long Term (2)

  12. Highlights of Plans for 2005 Lithography Update • Developed plan to determine effect of CD variability on device performance with Design, PIDS and FEP and to consider increasing CD tolerance to >10% • Agreed with FEP TWG on larger printed CD in resist • 1.6667physical gate length and 75%/25% variance allocation for lithography and etch, respectively • Propose to increase bias between size in resist and after etch for contacts • Propose definition of LWR and LER with Metrology TWG • Definition accounts for metrology, transistor and interconnect performance • Propose to tighten overlay tolerances • Propose to add lithographic tool field width and length into Table 77 • Update of potential solutions • Update of colors and values in mask and resist tables Proposal only; Not for publication

  13. Probable 2005 updates to the chapter test • Table showing progression of low k1 methods • DFM section to complement Design content • Automatic Process Control (APC) detail in chapter • Cost of ownership factors and throughput factors described in text Proposal only; Not for publication

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