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RIKEN/RBRC Itaru Nakagawa

Trigger Upgrade of PHENIX Muon Arms for Polarized Sea Quark Measurement and Background Study at  s=500 GeV. RIKEN/RBRC Itaru Nakagawa.  .  s=500 GeV @ RHIC. (LO). Parity Violation Asymmetry Clean flavor separation w/o fragmentation uncertainty. Projected Sensitivity @ PHENIX.

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RIKEN/RBRC Itaru Nakagawa

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  1. Trigger Upgrade of PHENIX Muon Arms for Polarized Sea Quark Measurement and Background Study at s=500 GeV RIKEN/RBRC Itaru Nakagawa

  2.  s=500 GeV @ RHIC (LO) Parity Violation Asymmetry Clean flavor separation w/o fragmentation uncertainty

  3. Projected Sensitivity @ PHENIX • Full Detector Simulation • S/B ~ 3/1 Assumed • 300 pb-1 and 1300 pb-1 Improvement in momentum resolution is underway

  4. Current Muon System Muon Tracking Chambers 3 stations of Cathode strip chambers 3 gaps + 3gaps + 2 gaps Each gap has non-stereo-plane, stereo-plane, and anode plane Slow read out -> No trigger Muon Identifier 5 layers of Iarocci tubes in x and y directions 80 cm of steel plate absorber (total) Provides trigger p > 1.5 GeV B   MuID MuTr St#1 St#2 St#3 Same configuration in South 4

  5. High Momentum Muon Trigger New Trigger Upgrade Run11 500 GeV Projection σtot=60mb L=1.5x1032cm-2s-1 Rate 9 MHz BBCMuID Rejection Power RP~100 Trigger Upgrade RP ~ 45 90 kHz RPtot ~ 4500 2 kHz PHENIX Band Width for Muon Required Rejection Power w/o Upgrade 5

  6. B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) ~10s Trigger MuTr FEE Interaction Region Rack Room

  7. B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes MuTr FEE 95% Interaction Region Rack Room

  8. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  9. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board Trigger RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  10. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board Trigger RPC FEE MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  11. Resistive Plate Counter (RPC) (Φ segmented) B W Trigger System (Final) Trigger events with straight track (e.g. Dstrip <= 1) Level 1 Trigger Board RPC FEE DCM DCM MuTRG Data Merge Amp/Discri. Transmit Trigger 5% Optical MuTRG MRG DCM MuTRG ADTX 1.2Gbps Trigger 2 planes RPC / MuTRG data are also recorded on disk. MuTr FEE 95% Interaction Region Rack Room

  12. Prototype RPC MuTRG MuTRG W Trigger Instrumentationin RHIC 2009 run absorber • Full Installation to North Arm, 1/2 octant installed to South • Demonstrate performance of RPC and MuTRG with beam of s=500 GeV.

  13. New MuTRIG-FEE in North Arm  Before Install 2008 Install

  14. MuTRG system Run09 performance trigger efficiency vs track momentum MuID trigger threshold plateau efficiency ~ 0.9  • MuID Algorithm • Track Matching w/ MuID • Timing cut w/ RPC • Track Matching w/ RPC • Background Shields • etc .. 14

  15. LL1 Trigger Readiness LL1 Board • Communication test  • LL1 Board Production by end of October • ADTX - MRG - LL1 - GL1 chain test this November. • New high momentum trigger will be operated in Run10 for commissioning MuTRG-MRG Boards

  16. Installation to South Muon Arm • Post Run9 Shutdown • Nearly Completed! • To be Commissioned in Run10 Au-Au Run

  17. Prototype RPC MuTRG MuTRG Road Map to Run11 Production Run absorber Run9

  18. MuTRG Road Map to Run11 Production Run RPC3 MuTRG Run10

  19. MuTRG Road Map to Run11 Production Run RPC3 RPC3 absorber MuTRG Run11

  20. MuTRG Final Muon Trigger Configuration RPC3 RPC3 absorber MuTRG RPC1 Run12

  21. Summary • Seak Quark Polarization Measurement @ PHENIX via W-Boson • High Momentum Muon Trigger is close to finish installation to MuTR FEE. • Run09 Commissioning demonstrated good efficiency&rejection factor. • Even more improvements are expected from • RPC (Timing & Matching) • MuID Algorithm • Background Shields PHENIX Muon Arms are getting ready for pp Production at 500 GeV in Run11

  22. Backup Slides

  23. High Momentum Muon Trigger New Trigger Upgrede MuID rejection in 200GeV and 500GeV rejection (MuID&BBC/BBC(nvtx)) 200 150 100 50 0 0 0.5 1.0 1.5 2.0 MHz BBC(nvtx) (estimated from ZDC narrow) w/o Upgrede • σtot=60mb, L=1.5x1032cm-2s-1 • rate = 9 MHz • DAQ rate limit < 2kHz (for muon Arm) • Therefore, required rejection power  2250 • MuID rejection power (RP) at 4.5 MHz < 50 • Additional RP~50 necessary Run11 500 GeV Projection 23

  24. Optical Alignment System Intrinsic MuTR Resition ~100 m Presentry 200 ~ 300m ` Yuki Ikeda and Kazufumi Ninomiya, Rikkyo University

  25. OASys Monitoring Thru Run09 IR Temperature Motion to phi Motion to r

  26. Vector and Magnitude of Motion

  27. MuTR Cross Talk

  28. A possible cross talk senario Particle hit the chamber and generate a electron-ion pairs in chambers. Electrons are collected by anode wire(s). It induces charge in near-by cathode strip(s) Collected anode charge does not have any path to escape in the anode circuit (high impedance). Other cathode strips induce same-sign charge in the strips, thus opposite sign charge in anode. After shaping, FEE sees cross-talk signals in opposite phase. +HV GND 28

  29. Rates per strip at 500 GeV (CLK trig) Average Station 3 Station 1 Station 2 Maximum Station 3 Station 2 Station 1 29

  30. Why this is bad? MuTr cathode signal Baseline-baseline ~10 msec Rate >100kHz at BBC=1MHz in 500GeV pp.  Pile-up regime ! Big pulse cause cross Talks btwn strips? 30

  31. Zero Suppression Hit distribution (200 GeV, zerosup OFF) Gap 1 Stereo Gap 2 Stereo Gap 3 Stereo Pedestal – ADC(3) Gap 1 NonStereo Gap 2 NonStereo Gap 3 NonStereo Strip mutr_strip_event000978_clk2424488676q 31

  32. MuTR Rates/Strip @ 500 GeV • Low energy hits from beam pipe? • Large pulse (20 MIP) in MuTR • Possbile cross talk causes high rate • Investigate sources Average Station 3 Station 1 Station 2 Maximum Station 3 Station 2 Station 1 MuTR Station-1 32

  33. RPC3 MuID on High Rates • Drawing Current Saturation at high rate.  Efficiency • Gap1,Gap5 > Gap2,Gap3,Gap4  RPC for Trigger  More Shielding?  shield Gap1,2,3,4,5

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