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1. Equipotentiality on the Grounded Surface

Lecture 8 : Equipotentiality and Current Coupling Richard Chi-Hsi Li 李缉熙 Cellular phone: 13917441363 (PRC) Email : chihsili@yahoo.com.cn. 1. Equipotentiality on the Grounded Surface o Equipotentiality on the Grounded Surface of a RF cable

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1. Equipotentiality on the Grounded Surface

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  1. Lecture 8 : Equipotentiality and Current Coupling Richard Chi-Hsi Li李缉熙 Cellular phone: 13917441363 (PRC) Email : chihsili@yahoo.com.cn • 1. Equipotentiality on the Grounded Surface • o Equipotentiality on the Grounded Surface of a RF cable • o Equipotentiality on the Grounded Surface of a PCB • o Possible Problems of a Large Test PCB • o Coercing Grounding • o Testing for Equipotentiality • 2. Forward and Return Current Coupling • o “Indifferent Assumption” and the “Great Ignore” • o Reduction of Current Coupling on a PCB • o Reduction of Current Coupling in a IC Die • o Reduction of Current Coupling between Multiple RF Blocks • o A Plausible System Assembly • 3. PCB and IC Chip with Multi Metallic Layers • Appendixes • A.1 Primary Considerations of a PCB Richard Li, 2008

  2. RF cable Ga Gb G1 G2 Figure 1 A regular RF cable 1. Equipotentiality on the Ground Surface oEquipotentiality on the Ground Surface of a RF Cable Questions Answers ? In most cases, ? In most cases, ? In most cases, Richard Li, 2008

  3. Vdd or Vcc E F PC B C A In Out B D Figure 2 Discussion of equipotentiality between points, A, B, C, D, E, F (The printed circuit on the PCB is neglected) Top metallic area Bottom metallic area 50 Ω runner Conductive via from top to bottom “Zero” Capacitor oEquipotentiality on the Ground Surface of a PCB Questions Answers ? In most cases, Richard Li, 2008

  4. DC Power Supply Signal Generator Spectrum Analyzer GP Power supply cable Vdd or Vcc E F GS Out In Multiple blocks or Complicated system A C B D GG Input RF cable Output RF cable G Figure 3 An example of test setup with a large PCB • Top metallic area; GG: Ground of signal generator • Bottom metallic area; GS : Ground of spectrum analyzer • Conductive via from top to bottom; GP:Ground of DC power supply • “Zero” capacitor; A, B, C, D, E, F, G : • SMA connector; Expected Ground points on PCB. o Possible Problems of a Large Test PCB Problems : Richard Li, 2008

  5. Top metallic area • Bottom metallic area “Zero” chip capacitors o Possible Problems of a Large Test PCB * To force the ground surface equipotential by “zero” chip capacitors vP1 ≠ vP2≠ vP3≠ vP4 P4 P3 P2 P1 PCB (a) Un-equipotentiality on a long runner, vP1 ≠ vP2≠ vP3≠ vP4 vP1 = vP2= vP3= vP4 P4 p P3 p P2 P1 p PCB p (b) Equipotentiality on a long runner resumed by “zero” capacitors, vP1 = vP2= vP3= vP4 Figure 4 Un-equipotentiality of a long runner changed to equipotentiality by means of “zero” chip capacitors. Richard Li, 2008

  6. vP1 ≠ vP2≠ vP3≠ vP4 P4 P3 P2 P1 PCB (a) Un-equipotentiality on large ground surface, vP1 ≠ vP2≠ vP3≠ vP4 vP1 = vP2= vP3= vP4 P4 P3 P2 P1 PCB (b) Equipotentiality on a large ground surface resumed by “zero” capacitors, vP1 = vP2= vP3= vP4 Figure 5 Un-equipotentiality of a large ground surface changed to equipotentiality by means of “zero” chip capacitors. • Top metallic area • Bottom metallic area “Zero” chip capacitors Richard Li, 2008

  7. Top metallic area • Bottom metallic area Micro strip line vP1 ≠ vP2 ≈vP3≠ vP4 P4 P3 P1 P2 PCB (a) Un-equipotentiality on a long runner, vP1 ≠ vP2 ≈ vP3 ≠ v4 vP1 = vP2 ≈vP3= vP4 λ/2 P4 P3 P1 P2 λ/2 PCB (b) Equipotentiality on a long runner resumed by λ/2 micro strip line, vP1 = vP2 ≈ vP3 = vP4 Figure 6 Un-equipotentiality of a large ground surface changed to equipotentiality by means of λ/2 micro strip line. Richard Li, 2008

  8. vP1 ≠ vP2 ≈vP3≠ vP4 P4 P3 P2 P1 PCB (a) Un-equipotentiality on large ground surface, vP1 ≠ vP2≈vP3≠ vP4 vP1 = vP2 ≈vP3= vP4 λ/2 P4 P3 p P2 p P1 p λ/2 PCB p (b) Equipotentiality on a large ground surface resumed by λ/2 micro strip line, vP1 = vP2≈vP3= vP4 Figure 7 Un-equipotentiality of a large ground surface changed to equipotentiality by means of λ/2 micro strip line • Top metallic area • Bottom metallic area Micro strip line Richard Li, 2008

  9. λ/4 • Top metallic area • Bottom metallic area Micro strip line vP1 ≠ vP2≠ vP3 P2 P3 P1 PCB (a) Un-equipotentiality on a long runner, vP1 ≠ vP2≠ vP3 vP1 = vP2= vP3 λ/4 P2 P3 P1 λ/4 PCB p (b) Equipotentiality on a long runner resumed by λ/4 micro strip line, vP1 = vP2= vP3 Figure 8 Un-equipotentiality of a large ground surface changed to equipotentiality by means of λ/4 micro strip line. Richard Li, 2008

  10. vP1 ≠ vP2 ≈vP3≠ vP4 P4 P2 P3 P1 PCB (a) Un-equipotentiality on large ground surface, vP1 ≠ vP2≠ vP3≠ vP4 vP1 = vP2 ≈vP3= vP4 P4 λ/4 λ/4 P2 P3 p λ/4 P1 PCB p λ/4 (b) Equipotentiality on a large ground surface resumed by λ/4 micro strip line, vP1 = vP2= vP3= vP4 Figure 9 Un-equipotentiality of a large ground surface changed to equipotentiality by means of λ/4 micro strip line • Top metallic area • Bottom metallic area Micro strip line Richard Li, 2008

  11. Network Analyzer Resultant RF cable Port 1 or port 2 (Readings of S11 or S22) Calibrated RF cable Port 1 or 2 Calibrated Point C Extented RF cable, Length = nλ/2 C Vdd A G In Out B Probe Figure 10 Testing of equipotentiality of a PCB Top metallic area Calibrated cable Bottom metallic area Extended cable Conductive via from top to bottom “Zero” Capacitor Grounding reference point, G C Richard Li, 2008

  12. Open Short Through (a) Calibrated cable (b) Calibration kit Figure 11 Calibrated cable and calibration kits for testing of equipotentiality of a PCB Calibrated cable Resistor 50 Ω Cable for calibration SMA connector 50 Ω Richard Li, 2008

  13. Forward currents flowing from positive pole of DC power supply to the circuitry through a cable or a wire Branch 2 Branch 1 Branch 3 Branch 4 Vddor Vcc L2 L7 R7 L5 R3 R5 R1 L1 L3 Out In Q3 Q4 Q2 Q1 G R2 L2 R4 L6 L4 R6 R8 L8 Return currents on grounded surface from the circuitry toward negative pole of DC power supply spread over the entire ground surface. Figure 12 Images of forward and return current between circuitry and DC power supply 2. Forward and Return Current coupling o “Indifferent Assumption” and the “Great Ignore” Richard Li, 2008

  14. Vdd P E F I1 I3 Q I2 L3 L1 L2 In Out M3 M2 M1 R2 L4 R4 L6 L5 R6 Branch 1 Branch 2 Branch 3 PCB Figure 13 Reduction of forward current coupling by means of “zero” capacitor” • Top metallic area; P : Point to be grounded; • Bottom metallic area; E, F : Well-grounded point. • “Zero” capacitor Forward current • Conductive via from top to bottom Return current • Magnetic flux o Reduction of Current Coupling on PCB Richard Li, 2008

  15. Vdd P E F I1 I3 I2 L3 L1 L2 In Out M3 M2 M1 R2 L4 R4 L6 L5 R6 Branch 1 Branch 2 Branch 3 PCB Figure 15.14 Reduction of forward current coupling by means of “zero” capacitor” • Top metallic area; P : Point to be grounded; • Bottom metallic area; E,F : Well-grounded point. • “Zero” capacitor Forward current • Conductive via from top to bottom; Return current • Magnetic flux Richard Li, 2008

  16. Vdd P E F I1 I3 I2 • Top metallic area; P : Point to be grounded; • Bottom metallic area; E,F : Well-grounded point. • “Zero” capacitor Forward current • Conductive via from top to bottom; Return current • Magnetic flux L3 L1 L2 In Out M3 M2 M1 R2 L4 R4 L6 L5 R6 Branch 1 Branch 2 Branch 3 PCB Figure 15.15 Reduction of forward current coupling by means of “zero” capacitor” Richard Li, 2008

  17. Vdd P E F I1 I3 I2 L3 L1 L2 In Out M3 M2 M1 R2 L4 R4 L6 L5 R6 Branch 1 Branch 2 Branch 3 PCB Figure 15.16 Reduction of forward current coupling by means of “zero” capacitor” • Top metallic area; P : Point to be grounded; • Bottom metallic area; E,F : Well-grounded point. • “Zero” capacitor Forward current • Conductive via from top to bottom; Return current • Magnetic flux Richard Li, 2008

  18. PCB (Printed Circuit Board) Chip “zero” capacitor IC die Figure 17 Reduction of forward and return current coupling simultaneously G Vdd RF Block Vdd Vdd Vdd Top metallic area; Bottom metallic area; Conductive via from top to bottom; “Zero” capacitor; Bonding pad; P+ guard ring; P : Point to be grounded; G : Reference grounded point; Forward current Return current Bonding wire; Metal layer in IC die L2 L2 Out L2 R1 R1 R1 In M3 M2 M1 R2 L3 L3 L3 R2 R2 P+ guard ring Branch#2 Branch#3 Branch#1 o Reduction of Current Coupling in a IC Die Richard Li, 2008

  19. o Reduction of Current Coupling Between Multiple RF Blocks • Providing DC power supply to blocks of circuitry separately; • Inserting long slots in the ground area so that each block has • its individual ground area. • All individual ground areas then are connected in parallel to • the common ground surface, which is equipotential with the • reference ground point at the power supply terminal. Richard Li, 2008

  20. Cover (Gold-plated) (Screw-connections with main body) Figure 18 Configuration of a “multi-closet” type of system assembly Block # 5 Block # 3 Block # 1 Block # 6 Block # 4 Block # 2 Vdd Block # 8 Block # 10 Block # 12 Block # 7 Block # 9 Block # 11 Main body (Gold-plated) o A Plausible System Assembly • Equipotentiality over the entire gold-plated surface of the box ? • Minimum of forward current magnetic coupling ? • Minimum of return current magnetic coupling ? Richard Li, 2008

  21. Cover (Gold-plated) (Screw-connections with main body) Figure 19 An improved connection path for power supply Block # 6 Block # 5 Block # 4 Block # 3 Block # 2 Block # 1 Vdd Block # 7 Block # 8 Block # 9 Block # 10 Block # 11 Block # 12 Main body (Gold-plated) Group A Group B Group C Richard Li, 2008

  22. Figure 20 An improved connection path for grounding Cover (Gold-plated) (Screw-connections with main body) Block # 6 Block # 5 Vdd Block # 4 Block # 3 Block # 2 Block # 1 Group B Group A Group C Block # 7 Block # 8 Block # 9 Block # 10 Block # 11 Block # 12 Main body (Gold-plated) Richard Li, 2008

  23. 3. PCB or IC Chip with Multi-Metallic Layers Advantages: Elimination of jumped wires • The connection between layers is made by conductive hole or via. Good isolation • RF and digital circuit blocks can be put on different metal layer; • An entire intermediate met layer can be specially applied as • a grounded surface between RF and digital circuit blocks; • A sensitive block can be “Sandwiched” by two grounded met layers. • And so on And so on Disadvantages: Expensive ! Q & A : • The ground surface is equipotential with the reference ground point, • the negative pole of DC power supply? • Forward and return current coupling are reduced to an insignificant level? • The RF signal with the highest operating frequency, which flows through • the conductive vias, does not have considerable attenuation? • The additional capacitance, inductance, and resistance due to the multi- • metallic configuration is insignificant? Richard Li, 2008

  24. Appendixes A.1 Primary Considerations of a PCB • How to select a PCB? • How to layout a PCB? • How to consider the size of a PCB? • How to handle a large PCB? • How to find the equipotentiality of the desired ground surface • and desired ground points on a large PCB? • Why does current coupling appear on the ground surface? • How to organize a multi-layers PCB? Richard Li, 2008

  25. Table 15A.1 Comparison of features between plastic and ceramic PCB • Plastic PCB Ceramic PCB • Processing time Couple hours processing Couple days processing • for two metal layers for top and bottom layer • Soldering of parts Couple hours Couple minutes • By soldering iron or machine By heating over an electric stove • Size Large Small • Mechanical property Robust and sturdy Fragile, easy to be broken • Cost Low High o Selection of a PCB • Type of PCB • Upper frequency limit • Number of metallic layers • Electromagnetic parameters Richard Li, 2008

  26. Vdd or Vcc PC B Wo W1 In Out D S Figure A.1 A preferred layout of a test PCB (The printed circuit on the PCB is neglected) Top metallic area Bottom metallic area 50 Ω runner Conductive via from top to bottom “Zero” Capacitor o Layout of PCB • Two metal layers is preferred • Conductive via • Diameter of via D > 10 mils. • Spacing between via S ≈ 4D to 10D • Special function of rectangular metallic frame on top Richard Li, 2008

  27. Figure A.2 Electric lines radiated either from the test circuit inside the PCB or from any interference • source outside the PCB would be terminated on the rectangular grounded frame. Electric line from inside Electric line from outside Imperfect grounding symbol DC power supply runner Top metallic area or runner Bottom metallic area Conductive via from top to bottom side Vdd Vdd Out Out. In In GND GND (b) Imperfect RF/AC grounding (a) Perfect RF/AC grounding Richard Li, 2008

  28. RFIC One RF Block G (b) Imperfect RF/AC grounding • Figure A2a Shielding effect of P+ guard ring Electric line from inside Electric line from outside Imperfect grounding symbol P+ guard ring RFIC--- One RF Block RFIC One RF Block G (a) Perfect RF/AC grounding Richard Li, 2008

  29. Spacing between the input or output runner and the adjacent grounded edge W1> 3 Wo. • Addition of “zero” capacitors • Others Richard Li, 2008

  30. o Size of PCB Small : L << /4 , Large: L~ or > /4 Richard Li, 2008

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