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Pixel hybrid status & issues

This presentation discusses the pixel hybrid overview and development at CERN for 10 years, including the ALICE1 readout chip and readout options at PHENIX. It also addresses other issues such as sensor development, ladder structure, and plans for the future. The presentation concludes with a summary of activities and the plan to install the barrel pixel layer in 2006.

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Pixel hybrid status & issues

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  1. Pixel hybrid status & issues K. Tanida (RIKEN)06/09/03 Si upgrade workshop Outline • Pixel hybrid overview • ALICE1 readout chip • Readout options at PHENIX • Other issues • Plans and activities

  2. readout chips sensor Pixel hybrid overview • Separated sensor and readout chip (bump bonded) • Development at CERN for ~ 10 years.- ALICE and other experiments • PHENIX plan- first barrel layer- may also be used for endcap pixels

  3. Ladder structure for barrel pixel • 8 chips/ladder + 1 pilot • 20 ladders  8192 x 8 x 20 = 1.3 Mchannel(occupancy ~ 1% for Au-Au central) ladder pixel chips optical link data bus with chip select pilot chip side view cross section

  4. Pixel chip (ALICE1 chip) 32 x 256 pixels of 425 mm (z) x 50 mm (rf) size: 13.6 mm x 15.95 mm

  5. Block diagram Preamp  shaper  discriminator  binary outputdelay unit for trigger latency 4 event buffer

  6. ALICE1 chip readout • 1 channel  1 bit (binary) • 32 parallel lines, each reads 256 channels serially • readout speed: 10 MHz 25.6 ms/chip- ALICE reads 10 chips serially via pilot chip  256 ms/event • ALICE1 has data buffer for 4 events • No data format (header, footer, parity bits ...)- must be taken care at somewhere (FEM?) • L1 trigger latency: 5.5 ms

  7. Pilot chip multi chip module • Takes care of readout, slow control (via JTAG), etc. • ALICE PCMCM: Consists of 4 parts- Analog pilot (A), Digital pilot (D), GOL (G), and optical link driver (O) • Analog pilot -- monitors temperature, etc. • G + O drives G link. Bandwidth: 1.28 Gb/s • Digital pilot -- main chip 15.5 mm D O A G 51 mm

  8. ALICE  PHENIX • What are different?- readout time (256 ms/event in ALICE, 40 ms in PHENIX)- event buffer (4 in ALICE1, PHENIX requires 5)- zero suppresstion, data format - L1 trigger timing (5.5 ms  4 ms) is OK. • Solution?- depends on readout time limit- parallelize readout (2 or more pilot chips in a ladder, sequential parallel readout, etc.)- development of our own pilot and/or other FEM necessary

  9. PHENIX readout options • Parallel readout- 8 chips  32x8 = 256 lines- digital pilot: FPGA, ASIC. How many?- data bus: higher density, more layers • Data transfer to DAQ- 8192×8 bit/event  1.6 Gb/s > optical link speed (ALICE: 1.28 Gb/s)- zero suppression at frontend: pilot or other FEM?- data format • Pilot chips and ladder bus options will bediscussed in the next talk.

  10. Other issues • Development of FEM + DCM • Heat load- ~ 1W/chip x 160 chips = 160 W requires liquid cooling • Bump bonding + thinning- wafer level bonding- thickness goal: 150 mm- ALICE is working on this RIKEN made a contract with ALICE ALICE will provide thinned, bump bonded chips

  11. Material budget • Goal: 1% radiation lengthSensor: 200 mm Si (0.22%)ALICE1: 150 mm Si (0.16%)ladder bus: 200 mm Al + kapton (~ 0.15%) mechanical support + cooling: 500 mm Carbon + ? (~ 0.3%)?glue: ~ 0.1%?

  12. Plans and actvities • Goal: to install barrel pixel layer in 2006. • 2003-4: prototyping- pilot chip (FPGA, ASIC): Iowa, RIKEN- ladder bus: RIKEN- cooling and meachanical design: LANL (Hytec), RIKEN • RIKEN-CERN(ALICE) contract- ALICE will provide bump-bonded thinned hybrids in 2003-2004.- Pilot chips and bus themselves are not included in the contract. • 2005-6: mass production

  13. Cost estimate Sensor + ALICE1 hybrid: 200 k$ Pilot chip MCM: 450 k$ (R&D) (185) Ladder: 550 k$ (R&D) (50) FEM +DCM: 205 k$ (R&D) (135) Total: ~1.4 M$ (0.4)

  14. RIKEN activities • CERN- J. M. Heuser, H. Onshi, and H. Kano participate in NA60 and ALICE- ALICE1 chip worked well in NA60- Learning pilot and bus technologies • KEK engineers are also participating • Wako- First bus prototype in Autumn 2003.- New pilot prototype in Autumn or in Winter.

  15. The NA60 Pixel Detector • pixel detector developed at CERN for application in ALI CE and LHCb. • ALICE1LHCb chip: 8192 pixels of 50 µm x 425 µm, radiation hard. • 16 NA60 specific 4- and 8-chip planes, 10 MHz clk, 200 ns strobe. • acceptance 3 <  < 4. • PCI readout by NA60. • Linux based DAQ. Hit map 1.0 cm June 2002 : the first 4-chip plane in 400 GeV/c proton beam 16-plane pixel detector telescope A cosmic ray in the 300 µm thin plane? The first 4-chip pixel plane

  16. NA60 Pixels – October 2002 • first three 4-chip pixel planes constructed. • test of vertex spectrometer with 20 and 30 GeV/c Pb beams on Pb targets, preparing for physics run in 2003. • tracking and vertex reconstruction with pixel planes.

  17. Summary • Conceptual design is almost done based on ALICE scheme. • Largest issue is readout speed pilot/bus modification is necessary • Prototyping has started. Continues until 2004. • Mass production is expected in 2005. • Our plan is to install barrel pixel layer in 2006.

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