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Architecture of Test Bench for the CISV module TE-MPE Technical Meeting

Architecture of Test Bench for the CISV module TE-MPE Technical Meeting Jakub Korczyc 1 st November 2012. Plan. CISV Module General Test Bench concept Hardware Software Test Bench architecture Hardware C ( LabWindows ) software FPGA firmware Test Bench capabilities

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Architecture of Test Bench for the CISV module TE-MPE Technical Meeting

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  1. Architecture of Test Bench for the CISV module TE-MPE Technical Meeting JakubKorczyc 1st November 2012

  2. Plan • CISV Module • General Test Bench concept • Hardware • Software • Test Bench architecture • Hardware • C (LabWindows) software • FPGA firmware • Test Bench capabilities • Test results CERN, the LHC and Machine Protection

  3. CISV Module • Part of the Safe Machine Parameters (SMP) system • Decodes 2 types of General Machine Timing (GMT) frames • Flags frames are decoded to LEMO outputs • Energy frames are transmitted through VME interface CERN, the LHC and Machine Protection

  4. General Test Bench - hardware • Common PXI crate and cards for general functionality • Custom made PCB for specific or time-crucial functionality CERN, the LHC and Machine Protection

  5. General Test Bench - software • C code template with common GUI and functionality • Excel file containing list of tests to run CERN, the LHC and Machine Protection

  6. CISV Test Bench - hardware • PXI Crate + Power Supply + Test Controller Card + VME rack • TCC based on Spartan 3 FPGA CERN, the LHC and Machine Protection

  7. CISV Test Bench - C software • Main concept: • use PXI controller to generate test vectors and analyze responses from the DUT • use Tester Control Card to pass on the data in time-deterministic way • Test campaign: • Generate all test vectors with time stamps. Sort them and store them on disc • Continuously send them to TCC. In the same time receive DUT responses with time stamps and store them on disc • Analyze stored responses CERN, the LHC and Machine Protection

  8. CISV Test Bench - C software • Advantages: • All complexity moved from VHDL to C code • VHDL code stays generic and test independent • Disadvantages: • Need for fast link between PXI and TCC CERN, the LHC and Machine Protection

  9. CISV Test Bench - FPGA firmware • Main functionality: buffering and timing CERN, the LHC and Machine Protection

  10. Test Bench capabilities • What it can do: • Send frames with maximum GMT speed • Run for about 12 hours with time resolution of 10μs (one frame takes 100μs to send) • Test 228 frames (one frame is 32 bits - 16bits of header and 16bits of payload) • Record every energy frame • Record flags values which are stable for 200ns • What it can not do: • Test not crucial functionality accessible by VME, like history buffer CERN, the LHC and Machine Protection

  11. Test results • Tested: • All energy values (216) • All flags values (28) • All headers (216) • Fail-safe values • Observations: • After power up, the CISV may ignore first few frames. Time between power up and receiving first frame does not matter. • There is 100μs delay in putting flags values after receiving the frame. • There is maximum 1ms delay in sending energy value after receiving the frame. CERN, the LHC and Machine Protection

  12. More information can be found on the website https://project-mitestbench.web.cern.ch

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