ASIC 120: Digital Systems and Standard-Cell ASIC Design

1. ASIC 120: Digital Systems and Standard-Cell ASIC Design Tutorial 2: Introduction to VHDL February 1, 2006

2. Outline • State Machines • HDL design flow • Format of a VHDL file • Combinational statements • assignments, conditionals, when … else • Sequential statements • processes, if … then … else

3. Summary of Previous Tutorial • Digital Systems • Combinational Logic • NOT, AND, OR, XOR, NAND, etc. • mux, half-adder, full-adder • Sequential Logic • flip-flop/register, shift register, counter

4. D Q D Q D Q D Q DFF DFF DFF DFF S C S C S C S C Clk Init Recall: Sequential Circuits • Sequential • computation involves a feedback loop (memory) • Example: ring counter

5. State Machines • We actually mean a Finite State Machine (FSM) • models behaviour • Components relevant to digital design • states • transitions • inputs • outputs

6. State Machines • Represented as a state diagram Transition State 1/0 0/0 S0 S3 Input 0/0 1/0 0/1 0/1 S1 S2 Output 1/1 1/1

7. 1/0 0/0 S0 S3 0/0 1/0 0/1 0/1 S1 S2 1/1 1/1 State Machines • Or as a state table Input A Output X

8. 1/0 0/0 00 11 0/0 1/0 0/1 0/1 01 10 1/1 1/1 State Machines • Encode states into binary Input A Output X

9. State Machines • Some things to note • we assigned S0 = 00, S1 = 01, etc., but state/bit mapping can be completely arbitrary • output is occurring on the transitions, this is called a Mealy state machine • where the output is dependent only on the current state, it is called a Moore machine

10. 1 00 (0) 11 (1) 0 1 0 0 01 (0) 10 (1) 1 State Machines • Remodelled as a Moore state machine Input A Output X

11. State Machines • This example is rather contrived • only dealing with abstract “states”, but imagine application to automatic door, traffic lights, etc. • Moore and Mealy machine looked the same • but they won’t always

12. 1/0 0/0 00 11 1 00 (0) 11 (1) 0/0 0 1/0 1 0/1 0 0/1 0 01 (0) 10 (1) 01 10 1 1/1 1/1 State Machines Mealy Moore

13. State Machines: Moore vs. Mealy • Mealy can often be represented using less states • transitions can produce different output • Even with more states, Moore often creates less hardware • less combinational logic • on an FPGA, registers (D flip-flops) are “free”

14. State Machines in Digital Hardware • This state machine requires two registers (D flip-flops), since there are four states • Basic procedure: • create state table • derive FF input equations (and output equations) from next state column with respect to present state and inputs • simplify equations • draw hardware

15. State Machines in Digital Hardware Let the two state bits (registers) be G and H • we also have input A G = GHA + GHA + GHA + GHA H = GHA + GHA + GHA + GHA X = G  H

16. State Machines in Digital Hardware Simplify the equations G = G  H H = GHA + A X = G  H

17. D Q D Q DFF DFF State Machines in Digital Hardware A Draw the hardware G = G  H H = GHA + A X = G  H A G H X Clk

18. State Machines in Digital Hardware • I’ve skipped many details and nuances • see ECE 223 course notes • State machines can get very complicated • often don’t work out states in this detail • let synthesis tools do it

19. Optimization of State Machines • Outside the scope of this tutorial • Summary • reduce number of states by combining states, while preserving equivalent functionality • bit encoding can affect the size of the circuitry generated to implement it

20. D Q D Q D Q D Q DFF DFF DFF DFF S C S C S C S C Clk Init Ring Counter • Is this a state machine? Yes: every sequential circuit is a state machine

21. Back to Register Transfer Level (RTL) Logic Sequential Feedback Data Out Data In Register Register Register Cloud of Logic Cloud of Logic Clock Combinational

22. Hardware Description Languages (HDLs) • HDLs describes in text a digital circuit • Examples • VHDL (we will look at this next time) • Verilog • AHDL • JHDL

23. Hardware Description Languages (HDLs) • schematics are useful for… • drawing high level diagrams • manually working out simple pieces of logic • HDLs are useful for… • describing complex digital systems • HDLs are not... • software programming languages (C, Java, assembly, etc.)

24. Think Digital • When designing a digital system in VHDL, it is important to remember the relation between code constructs and actual hardware

25. HDL Design Flow • Concept, requirements analysis • High level design • Functional implementation (need not be synthesizable) • Functional simulation (3 -> 4 until functionality is good) • Synthesizable implementation • Synthesizable simulation (6 -> 5 until functionality is good) • Timing simulation (7 -> 5 until timing is good; this step I often bypassed in practice) • Synthesis • design is compiled to hardware • we will cover this in more detail later • 8 -> 5 if design doesn’t compile or doesn’t fit • Testing in hardware (9 -> 5 if something is wrong)

26. What does “synthesizable” mean? • Synthesizable means that a given design can be compiled into hardware • FPGA (reprogrammable ASIC) • ASIC • A non-synthesizable design can be simulated in software and is useful for • working out functionality • testing out concepts • test benches (covered in detail later)

27. Levels of Abstraction • Behavioural • Dataflow • Structural

28. Components of a VHDL File • library • ieee, etc. • use • entity • defines the interface • architecture • defines the functionality • component • reusable functionality • multiple entity/architectures in one file

29. Why do we use IEEE libraries? • standard VHDL libraries are limited to two values: 0 and 1 • this is fine for theory, but in practice a physical wire can have other values • more on this in later tutorials

30. Inputs and Outputs • declared in the entity • the “pins” of the hardware block • can only be input, output, or I/O • output pins cannot be read from • for example, if I assign a value to an output pin I cannot “read” that value back in another place • output pins are like black holes in this way

31. Signals • Signals are the internal “wires” of your design • Can be assigned a value, or have their value read • Signals can be read in multiple places, but assigned in only one place • “cannot have multiple output pins driving a wire”

32. Buses • Provide an easy way to group multiple signals or ports

33. Combinational Logic • In VHDL: “Concurrent Statements” • Remember: all functionality is defined within architecture block • Order doesn’t matter • Types of concurrent statements • assignments • conditional assignments • processes

34. Combinational Assignments destination <= source_logic; examples: X <= A AND B; Y <= NOT (A AND B); Z <= A XOR B AND C NOT B;

35. Conditional Assignments destination <= source_logic_1 when condition_1 else source_logic_2 when condition_2 else source_logic_3; example: X <= A AND B when Sel = “00” else NOT (A AND B) when Sel = “01” else A XOR B when Sel(0) & Sel(1) = “10”

36. Conditional Assignment: A MUX • Conditional assignments are modelled physically as a multiplexer X <= A AND B when Sel = “00” else NOT (A AND B) when Sel = “01” else A XOR B when Sel(0) & Sel(1) = “10” A B 00 01 X A B 10 11 Sel(0) Sel(1) Sel

37. Brackets and The & Operator • Brackets • used to reference parts of buses • & Operator • signal concatenation operator • used for constructing buses out of single wire signals, or parts of other buses

38. Processes • Contain chunks of VHDL code • Can be purely combinational • Most useful for sequential logic • controlled by a clock • processes are executed in parallel, in any order • Processes can optionally be named

39. Process Statement [process_name:] process (sensitivity_list) declarations begin sequential_statements end process;

40. Sequential Logic • In VHDL: “Sequential Statements” • Within a process, statements execute sequentially • important to remember that logic is tied back to underlying hardware

41. If … Then …Else Statement • Like the concurrent “when … else” statement, modelled as a multiplexer iffirst_conditionthen statements elsifsecond_condition then statements else statements endif;

42. MUX with an If Statement     process(Sel, A, B, C, D)     begin         if Sel = "00" then             Y <= A;         elsif Sel = "01" then             Y <= B;         elsif Sel = "10" then             Y <= C;         elsif Sel = "11" then             Y <= D;         end if;     end process;

43. MUX with an If Statement • Note that this mux is a combinational mux • i.e., not governed by a clock A 00 B 01 Y C 10 D 11 Sel(0) Sel(1)

44. Clocked Processes • Or: “Sequential Processes” • Consider a “clocked mux”:     process     begin wait until rising_edge(Clk);         if Sel = "00" then             Y <= A;         elsif Sel = "01" then             Y <= B;         elsif Sel = "10" then             Y <= C;         elsif then             Y <= D;         end if;     end process;

45. D Q DFF Clocked Processes • Or: “Sequential Processes” • Consider a “clocked mux”:     process     begin wait until rising_edge(Clk);         if Sel = "00" then             Y <= A;         elsif Sel = "01" then             Y <= B;         elsif Sel = "10" then             Y <= C;         elsif then             Y <= D;         end if;     end process; A 00 B 01 Y C 10 D 11 Sel(0) Sel(1) Clk

46. Clocked Processes • Statements are essentially executed in series • Important to always keep in mind underlying hardware

47. Clocked Processes • Consider:     process     begin wait until rising_edge(Clk);         if Sel = ‘0’ then             Y <= A; else             Y <= B;         end if;         if Sel = ‘0’ then             Z <= B; else             Z <= A;         end if;     end process;

48. D Q D Q DFF DFF Clocked Processes • Consider:     process     begin wait until rising_edge(Clk);         if Sel = ‘0’ then             Y <= A; else             Y <= B;         end if;         if Sel = ‘0’ then             Z <= B; else             Z <= A;         end if;     end process; A 0 Y B 1 Sel Clk B 0 Z A 1 Sel Clk

49. D Q D Q DFF DFF Clocked Processes • This code produces the same hardware:     process     begin wait until rising_edge(Clk);         if Sel = ‘0’ then             Y <= A; Z <= B; else             Y <= B;             Z <= A;         end if;     end process; A 0 Y B 1 Sel Clk B 0 Z A 1 Sel Clk

50. Remember • Always consider the underlying hardware! • ask yourself: what does the VHDL code I’m writing actually represent?