Local Trigger Unit for NA62

1. Local Trigger Unit for NA62 Marián Krivda1) , Cristina Lazzeroni1) , Vlado Černý2), Tomáš Blažek2), Roman Lietava1)2) 1) University of Birmingham, UK 2) Comenius University, Bratislava, Slovakia

2. Content • General view • Status of LTU production and tests • Status of firmware • Status of software • Usage of LTU boards for Run2011 • News from TTC upgrade meeting • Summary

3. Clock distribution and data flow Triggers Sync. card 40 MHz clock source Trigger inputs L0TP CHOKE/ ERROR TTC Clock + Triggers TTC partition LTU + TTCex LTU + TTCex LTU + TTCex LTU + TTCex . . . . . . . . . . . . . . . . . . . . . . . TTCrx TTCrx TTCrx TTCrx . . . . . . . . . . . . . . . . . . . . . . . QPLL QPLL QPLL QPLL FEE FEE FEE FEE For jitter < 50 ps RMS QPLL must be used !

4. LTU+TTCex+(20dB att./TTCoc) 6U VME cards 1 LTU+TTCex per detector !!! Optical transmission of A and B channel TTCex Local Trigger Unit LTU Monitoring of TTC TTCit TTCoc 1:32 Trig. data from L0 processor LVDS (7) Burst Warning ejection (WE) Detector CHOKE/ERROR 31 optical outputs to FEE ser. data channel A ser. data channel B clock clock 40 MHz clock source

5. Status of LTU production and tests • First 3 LTU boards are produced • 3 faulty components LMS1583-1.5 • 2 faulty components PDU15F • 1 PCB damaged by replacing the faulty component

6. Status of LTU production and tests • Problems after replacement of one faulty component (2 unconnected pads and microscopic hole)

7. Status of LTU production and tests • Performed tests • VME FPGA connections • LTU FPGA connections • Flash Memory test • SnapShot memory test • LEDs test • Front panel connectors test

8. LTU testing software: LTU main components FLASH MEMORY stores code to be loaded into LTU FPGA FRONT PANEL I/O connectors LTU FPGA LTU logic VME BUS FRONT PANEL OSCILOSCOPE connectors VME FPGA basic "firmware" Snap shot memory • Computer speaks via VME bus to VME FPGA which distributes the communication further to inner LTU parts • LTU FPGA is programmed to perform LTU logic operations • The LTU logic reacts to control commands from computer (by for example sending a signal from a particular point inside LTU into front panel I/O connector or sending the value back to computer via VME FPGA and VME bus • Snap shot memory to provide the possibility of logging of 26 ms of the front panel data • The testing software tests the communication between those main blocks

9. LTU testing software: Testing procedure Testing software guides the operator via screen prompts like "Connect the oscilloscope to connector B" "You should see clock signal" "Press enter when ready“ Phase 0: Testing that LTU (VME FPGA) reacts to VME bus Phase 1: tests the flash memory writing and reading back random data Phase 2: loads phase 2 logic into LTU FPGA checks success of PLL clock lock tests snap shot memory by writing and reading back random data tests that data logging into snap shot memory is functional Phase 3: loads phase 3/4 logic into LTU FPGA test R/W operations to LTU FPGA Phase 4: sending various signals to specific front panel connectors and testing their presence by oscilloscope

10. News from TTC upgrade meeting • PHOTON lasers replace by OCP lasers (300 USD/pc), median life of OCP estimated to more than 88 years • possible replacement of TRR1B43 by PD-LD (68 EUR/pc) or Ficer (28EUR/pc), to be qualified early 2011 • new TTCex: 1. New PLL to replace obsolete VCXO 2. Standalone frequency compliant with QPLL locking range 3. Ability to turn on-off each laser individually and monitor their status 4. Available in January 2011 • possible replacement of TTCrq board with TTC-FMC board, ref. design (HW + Firmware) in 2011, better connector, 2 ways (TTCrq flavor, Light flavor)

11. Usage of LTUs for Run2011 40 MHz clock source ECL fan-out Trigger inputs • Usage of PULSER (ECL) input on LTU board TTC partition LTU + TTCex LTU + TTCex LTU + TTCex LTU + TTCex . . . . . . . . . . . . . . . . . . . . . . . TTC Clock + Triggers TTCrx TTCrx TTCrx TTCrx . . . . . . . . . . . . . . . . . . . . . . . QPLL QPLL QPLL QPLL FEE FEE FEE FEE

12. Status of firmware • Written some modules in Verilog (ALICE LTU is wiritten in AHDL) l0_logic (top module), pll, led, clock_check, gray_counter, gray2bin, adc, busy, ttcvi_emu, vi_fifo1024x6, l0fifo_write, l0_fifo • Simulations in CADENCE

13. Status of software • Reminder: DIM architecture • DIM servers running on VME processor in the crate • DIM clients running anywhere in the world • All services implemented on both the client and server sides • Adapting to details of the new NA62 LTU firmware will be done in a short time after the firmware is ready • New stuff: SIM proxies to provide interface to RUNCONTROL and/or DCS

14. SMI DOMAIN "SMI_LTU" SMI GUI DIM clients Ob Obj Obj Obj TCP/IP CEDAR VETO VMEprocessor VME driver LTU LTU LTU DIM/SMI proxy DIM/SMI proxy DIM/SMI proxy DIM/SMI architecture STRAW

16. Summary concerning SMI • What we presented here is a proof of concept. Details concerning SMI objects and actions are to be discussed with RUNCONTROL programmers. • We are able to provide SMI proxies to be connected to (maybe third party) SMI managers • We are ready if it is decided that RUNCONTROL and/or DCS would be based on SMI

17. Summary • We have asked to produce next 2 LTU boards in order to check quality of production • If there will be any faulty component we will send the board back to company for replacement • Basic firmware and software for testing of components on the LTU is ready • Final firmware written in Verilog, partially done, simulation in CADENECE set-up.