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L0 processor for NA62

L0 processor for NA62. Marian Krivda 1) , Cristina Lazzeroni 1) , Roman Lietava 1)2) 1) University of Birmingham, UK 2) Comenius University, Bratislava, Slovakia. Content. Requirements Block diagram Board layout and front panel Trigger message from each sub-detector

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L0 processor for NA62

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  1. L0 processor for NA62 Marian Krivda 1) , Cristina Lazzeroni 1) , Roman Lietava 1)2) 1) University of Birmingham, UK 2) Comenius University, Bratislava, Slovakia

  2. Content • Requirements • Block diagram • Board layout and front panel • Trigger message from each sub-detector • L0 processor implementation • T0 time definition • T0 timeout • Summary

  3. Requirements • 8 triggering detectors • Trigger input signals are asynchronous messages (send over gigabit Ethernet) • From each triggering detector - timestamp (BC/256) + 8-bits for type of trigger • Trigger data for TTC must be synchronous • Burst input • Warning ejection – WE, WWE inputs • BUSY/ERROR input from each LTU

  4. Block diagram Triggers L0 processor 40 MHz clock source Trigger inputs BUSY/ ERROR Clock + Triggers LTU + TTCex LTU + TTCex LTU + TTCex LTU + TTCex . . . . . . . . . . . . . . . . . . . . . . . TTCrx TTCrx TTCrx TTCrx . . . . . . . . . . . . . . . . . . . . . . . QPLL QPLL QPLL QPLL FEE FEE FEE FEE

  5. Possible solution for L0 processor 6U VME cards – L0 processor, BUSY fan-in Fan-in unit BUSY FI LTU1 LTU2 LTU3 LTU16 16 x LVDS flat cables to LTUs ……………. Burst WE BUSY clock 40 MHz clock source

  6. 6U VME crate VME Master L0 processor BUSY FAN-IN TTCex 1 TTCex 2 TTCex 3 TTCex 4 TTCex 8 LTU 1 LTU 2 LTU 3 LTU 4 LTU 5 TTCex 5 LTU 6 TTCex 6 LTU 7 TTCex 7 LTU 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

  7. Board layout (6U VME) 16 x LVDS – flat cable to LTUs VME connectors FPGA 8 x Ethernet from triggering detectors RAM Burst, WE, WWE 8 x BUSY

  8. Trigger message from triggering detector FE send trigger message asynchronously (GigaBitEthernet) in following format: • fine time: 8 bit • timestamp (40MHz): 32 bit • trigger type (L0): 8 bit

  9. L0 processor (LOP) L0 processor receives FE trigger messages and: • according to timestamp identifies messages from same interaction • not later then given time T0 • evaluates programmable logical combinations of trigger types • sends synchronously readout trigger strobe and messages (40MHz) via TTC

  10. L0 processor implementation • Data from triggering detectors are stored in memory position following the time stamp • After T0 time (timeout for receiving trigger data) L0 processor will make decision and can rewrite this position in memory with new data if they are already available • Zero suppression is maybe also possible

  11. T0 time • When “start of burst” => T0 counter reset • Then it counts with 40 MHz clock • T0 time/timeout manages that trigger data are sent to LTUs/TTC synchronously

  12. T0 timeout • It is maximum time difference between arrivals of trigger messages from the same interaction to L0P. • It is determined by: • FE (< 100 ns) • topology of detectors (max < 100m*4 ns/m=400ns) • Ethernet protocol (???)

  13. Summary • Completely new L0 processor board is probably better solution then reuse some old card with new mezzanine cards. A cost for 6U VME board should be lower than in example TELL1 + new mezzanine cards • We need 2 x 6U VME crates for TTC + L0 processor • We can start a test with Altera Stratix III Evaluation board, where is Ethernet and memory

  14. Back-up

  15. TDAQ trigger design 1.) TTC distributes a clock (BC) 2.) Fine time: FEE runs BC, and also clock 40Mhz/256 3.) Time stamp : # counts of BC from start of burst - BC stamp Readout time information: # of fine clocks from timestamp 4.) Trigger input signals are asynchronous messages (send over gigabit Ethernet). They contain timestamp (BC) of event which produced trigger. 5.) CTP: runs BC, receives messages, decode them and if condition fulfilled CTP sends readout trigger over TTC (triggers are send synch., trigger message is sent asynch.) 6.) FEE receives trigger and reads events corresponding to the all BC period (25ns) or more. Events are then composed offline (or in daq) analyzing time information (fine time and time stamp)

  16. Algorithms for generating trigger • Timeout T0 : • It is maximum time difference between arrivals of trigger messages from the same interaction to L0P. • It is determined by: • FE • topology of detectors • Ethernet protocol • Algorithm: • save incoming triggers in memory position wrt to its time stamp • at time T0 take all triggers at same memory position (= time stamp) • and evaluate them for trigger conditions • send readout triggers via TTC at fixed time wrt to interaction

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