1 / 11

Data Controller Board Preliminary Design Review Dorothy Gordon University of California - Berkeley

Data Controller Board Preliminary Design Review Dorothy Gordon University of California - Berkeley. Overview. Data Controller Board Requirements & Specifications Block Diagram Electrical Diagram Layout Mass and Power Parts Schedule Issues. Requirements & Specs. Basic Subsystems

zenia-larson
Download Presentation

Data Controller Board Preliminary Design Review Dorothy Gordon University of California - Berkeley

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Data Controller Board • Preliminary Design Review • Dorothy Gordon • University of California - Berkeley

  2. Overview • Data Controller Board • Requirements & Specifications • Block Diagram • Electrical Diagram • Layout • Mass and Power • Parts • Schedule • Issues

  3. Requirements & Specs • Basic Subsystems • C&DH interface • Commands arrive via UART (38.4Kbaud) • 1Kbytes/second + header & checksum • “Low-speed” telemetry transmitted via UART (38.4Kbaud) • Housekeeping/SOH and FGM engineering data (total of ~150bytes/sec) • “High-speed” telemetry - 2 Mbps • Science data - CCSDS packetization & transmission to BAU • Solid state recorder (SSR) • Provides 256Mbytes of raw SDRAM • Upper quadrant is devoted to ECC • Instruments - Mode Setup and Data Ingest • Instrument initialization parameters as outlined in ICDs

  4. Requirements & Specs • Basic subsystems (continued) • Time management • Receives 223clock and 1Hz synch from spacecraft • Forwarded to Electric Field Instruments • Clocks internal DCB timebase counter - used to time-tag packets as they are written into the SSR • Receives Sun Pulse from Spacecraft • Computes Spin Synch & Spin Sector Pulses (forwarded to Particle Instruments) • Housekeeping • Instrument analog lines routed to housekeeping ADC • DCB samples data at regular intervals; information forwarded to the spacecraft via the low-speed telemetry I/F

  5. Block Diagram

  6. Electrical Diagram

  7. Layout

  8. Power • Required Voltages • Digital supplies: 5V, 3.3V and 2.5V • 3.3v created by on-board linear regulator • Analog supplies: +10V, -10V, +5V, -5V • Estimated Power Usage • 1W. Average, 3W. Peak • Peak figure includes bipolar PROM, which is turned off after processor initialization • Most current drawn by: FPGA, SDRAM (& linear regulator), and SRAM

  9. Parts • Main Components • Processor - Harris 80C85 • Boot ROM - Raytheon R29793 • FPGA - Actel 54SX72s • SRAM - SEU immune (128Kx8) - Honeywell 6228 • SDRAM (256M x 8) - 3D-Plus stacked module • EEPROM (128Kx8), Maxwell 28C011 • Analog-to-Digital Converter - LTC1604 • Voltage Regulator (5V - 3.3V) - OMR9808SF • Translators/Buffers - Maxwell 54LVTH series • ETU & Flight Part Ordering • In some cases, commercial equivalents used on ETUs • Most long-lead time components have been ordered (for both flight and ETU systems)

  10. Schedule ETU - PCB Layout in November, Fabrication/Population in December (concurrent with FPGA design) Initial DCB Test targeted for late Dec’03 through Jan’04

  11. Issues • Schedule • Ambitious - no room for the unexpected

More Related