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IDPU Flight Software Preliminary Design Review F. Harvey University of California - Berkeley. Overview. Flight Software Overview Requirements v Design Documentation Design Modes Timing & Sectoring Command Reception State of Health Telemetry Deployments, Attenuators, Enables
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IDPU Flight Software • Preliminary Design Review • F. Harvey • University of California - Berkeley
Overview • Flight Software Overview • Requirements v Design • Documentation • Design • Modes • Timing & Sectoring • Command Reception • State of Health Telemetry • Deployments, Attenuators, Enables • Data Collection, Analysis, Compression • Science Telemetry • Science Modes & Triggers • Resource Summary • Schedule • Issues
Documentation • FSW Primary Documentation FSW Technical Notes
Documentation • FSW Reference Documentation
Modes • FSW Modes • Safe • Normal • Engineering • Safe Mode • FSW Reset into Safe Mode • All instrument Power Disabled • Useful for Power Emergencies on Probe • SSR retains all data • Engineering Mode • Deployments & Some Actuators Are Enabled
Timing • Timing Interrupt • FSW Background Structured on 256 Hz Interrupt • BKG Module Distributes CPU Time to Other Modules • Basic ¼ second Mapping of Functions Planned e.g. • Command Module Programmed for 64 Hz • DFB Packet Management for 32 Hz • Guarantees 4 msec response to events • Typical CPU Required appx 7 to 10% in Background
Sectoring • Spin Sectoring • FSW Reads Sun Pulse and Spin Reference Pulse Times • Determines Spin Period and SP-SRP difference • Sets 8MHz-Divide-by-N Register to Generate 2^14 Sectors • Changes Divide-by-N to N+1 in Mid-spin • FSW Allows Injecting Phase Offset (Target=Sun+offset) • Free Runs in Eclipse, No Update to Spin Period • Relatively Insensitive to Latencies
Command Reception • Command Reception (38.4K) • DMA Input in 1008 byte Blocks containing multiple Command Packets • FSW Checks/Decodes each Packet in the Block • Each Packet is either Command or Memory Load (Apids 400 and 401) • Command Packets are Strings of 16-bit Command Codes • Command Codes are Executed at 64 Hz • Command Counter to Verify Long Loads • Command Channel Capacity (Uplink & ATS) is Managed by FOT
Command Reception • Command Reception • Memory Loads Include Address and Length • Variable Size Loads up to 255 bytes per packet • If EEPROM is ON & enabled, can directly load EEPROM
State of Health Telemetry • State of Health Telemetry (38.4K) • Recorded in Probe Memory in case of IDPU Power Down • Double Buffered Generation & Transfer • Generated During One Second & Sent the Next Second to Probe • Can be Decimated by Probe to Achieve Down to 64 bps Rate • All Quantities Can be Sampled at 1/16th rate and Still be Understood
Deployments • Spin Plane Booms • DEP Module Controls Spin-Plane Booms Deployment Motors • Deployment Enable Must be Commanded On • Same module as used on CRRES (2), Polar(4), Cluster(16) • Will Deploy One Axis at a Time (in Pairs) or One at a Time • Monitors Turns Clicks (10cm/click ~ 5 seconds per ½ click) • Fail-Equal Strategy : Always Keeps Boom Lengths within 2 Clicks • Pauses a Motor on a Fast Boom and Waits for Slower Boom to Match • Axial and Mag Booms • Deployment Enable Must be Commanded On • Mag Booms are Released by N seconds of Power to Frangibolts • Mag Booms have Primary and Redundant Actuators • Axials are Released by N seconds of SMA Power • Axials are Independently Controlled • ESA Cover Release • ESA SMA Enable Must be Commanded On • Cover is Selected and Released by Separate Commands • FSW delivers timed pulse (~2 second)
Attenuators • ESA Solar Wind Attenuator • PWR Module provides SWA Open & Close Commands • ESA SMA Enable Must be ON (Science or Engineering Modes) • PWR Module Gives Timed Pulse to ESA (1 second) • Status of SWA Sampled and Returned in SOH Telemetry • SST Attenuator • PWR Module provides Attenuator Open & Closed • Both SST1 and SST2 Operated Together • SST Atten Enable Must be ON (Science or Engineering Modes) • PWR Module Gives Timed Pulse to SSTs (1 second) • Status of Attenuators Sampled by ETC Circuit and Returned in Science Telemetry • Attenuator Relaxation • FSW Implements 60 second non-op period to allow cooldown between actuations
Enables • Enables Register • Mask Applied by Mode • Enables Masked Off in Safe Mode, etc
Data Collection • Data Collection • DMA Channel Controller Assigned to Each Data Source • FSW Hands Packet Addresses to Each DMA Channel Controller • Double-Buffered DMA Address to Eliminate Gaps • DMA Channels Are Sync’d to either Time or Spin-Phase • FSW Initializes Each DMA Channel for type of Synchronization • FSW writes Headers for Each Packet as it is Produced • Data Collection Rates • Peak Input Rate of 430 KB • Preferred Length just under 4 KB for raw data packets • Peak Packet Rate of 157 Packets/sec • Performance Calculation: ~300 cycles/header, ~2.4% CPU
Data Collection • DMA Channels
Data Collection • DMA Channels
Data Analysis • On Board Data Analysis – E & B Spin Fits • Spin Fit Calculations are Performed on DFB and FGM data • 32 16-bit data points are taken at Equal Angles and Stored in Array • Spin Fit is Performed to Reduce 32 samples to Offset, Sine & Cosine terms
Data Analysis • On Board Data Analysis – E & B Spin Fits • Spin Fit Matrix • Results are A, B, C, Sigma (floating point), N (1 byte) • Fast Flt Point = 1 sign bit, 7 exponent bits, 16 mantissa bits • Each E&B fit timed with Tsun & Tsrp (xx.yyyy format) • Each Spin Generates 3+3+13+13 = 32 bytes • Spin Packet is 112 Spins or 3586 bytes (before compression) • Performance: Fit Requires 7.2e+5 cycles (360 msec)
Data Compression • Data Compression • Multiple Algorithms Available (ref. thm_fsw_901_Compression) • Huffman4 • Delta Modulation • Combined Delta Mod/Huffman • Run Length not effective on this data • Numerous Studies of Compression Algorithm Performance • Used Cluster Flight Data • Similar Instrumentation, Expected Signal Levels • Similar Data Volumes • Achieved appx 1.5 compression without being Adaptive • High Rate (Burst) sampling Compresses > 2 • Performance Studies of Non Adaptive Compressors • Huffman4x2 Algorithm 21 KB/sec • Delta Modulation Algorithm 11-14 KB/sec • Entire Memory Compressed in 1-2 hours
Science Telemetry • Science Telemetry (2Mbps) • Packets Selected are Handed to DCB High Speed TLM DMA • Address of the 4K Block and Length in Bytes • FSW receives Interrupt when the Address Pointers Swap • FSW has 1 Packet Time to refresh DMA Address Pointer • Packet Rate Determined by Packet Length • If Packets are 2-4KB in length, then at 2Mbps transfer rate, FSW outputs ~50 to 100 packets per sec. • If Packets are Compressed, then FSW may find very short packets. • Packet Mixing • FSW will mix real-time diagnostic packets (if needed) into the High Speed TLM line. • Single VC simplifies hardware design
Science Modes • Science Modes • Slow Survey (SS) • Fast Survey (FS) • Particle Burst (PB) • Wave Burst (WB) • Mode Control • SS-to-FS by ATS Command • FS-to-PB when Trigger_Eval > PB_Thresh • PB-to-WB when Trigger_Eval > WB_Thresh • Transitions Achieved Using Command Strings • WB1 and WB2 Are Implemented by Different Uplink Configurations • Return When Eval Goes Below Thresh by 12.5% or Over Memory Allocation
Triggers • Trigger Calculations Use In Situ Data • FSW Continuously Samples Science Data in SSR (e.g. ESA/SST Peak Flux, DFB V1-V6 Voltages, FGM Bx-Bz) • Evaluates Data Quality at 8 Hz • Calculates Quality using 8 Selectable Functions • Result Values 0-255 • Specific Functions are TBD (Phase IV) • Conjunction Prioritization • FOT will uplink Predicted Conjunction Times • FSW increases Quality Evaluation near Conjunction • Conjunction Duration and Bias are Commandable
Resources • PROM/EEPROM • PROM Functions • EEPROM Load • Uplink Support • Basic Functions • EEPROM/Uplink • One-Time Events • Test Programs • Initialization Parameters • Science Upgrades • Recommended Minimums • 8-16K PROM • 64K EEPROM
Resources • RAM Requirements • RAM Functions Holds Code Image in RAM (8-12K) Variables • Max of Prior Projects appx 6K (HESSI 2.5 K, Cluster 3.5K, FAST 5.8K) Total Required of appx 14-18K • RAM Provided (SRAM) 32K Directly Addressable (~100% margin) 128K Page Addressable
Schedule • Development Plan THM_FSW_004 Describes Development Plan Phased Development Used in HESSI and FAST • Phase I – Board Level • Phase II – Box Level • Phase III – Instrument Level • Phase IV – Science Optimization FSW ETU Schedule FSW ETU Phase I Board Lvl Development 10/7/03 12/1/03 FSW ETU Phase I Test 1/19/04 2/2/04 FSW ETU Phase II Box Lvl Development 12/2/03 1/12/04 FSW ETU Phase II Test 2/2/04 2/23/04 FSW ETU Phase III Inst Lvl Development 2/25/04 4/6/04 FSW ETU Phase III Verification w Sims 4/7/04 4/20/04 FSW FLIGHT Schedule FSW FLT SPEC MODS 6/8/04 6/21/04 FSW FLT Development/Test 6/22/04 7/19/04 FSW FLT PROM FINAL 7/20/04 7/20/04 FSW ETU Phase IV Science Development 7/21/04 9/14/04 FSW ETU Phase IV Test 9/15/04 10/12/04
Issues • Issues • Need Initial Parameter Load Details for ETC