VHDL Development for ELEC7770 VLSI Project

1. VHDL Development for ELEC7770 VLSI Project Chris Erickson Graduate Student Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 Chris.Erickson@auburn.edu

2. Objectives • Logically perform the designed functions • Be efficient • Code length • Routines • Signal utilization • Perform the functions appropriately per cycle

3. Component Development All components designed & developed independently • Instruction Register • Program Counter • Register File • Data Register • Multiplexers Test RS A Test RT Register File Test RD B Test RegWrite

4. Multicycle Datapath Cycles per instruction (CPI): • Load Word 5 • Store Word 4 • Register-type 4 • Branch 3 • Jump 3

5. 3 to 5 Cycles per instruction

6. Instruction decode Instruction fetch ALU operation Write PC on branch condition Write PC on jump Compute memory addr. Write memory data Read memory data Write register Write register Control FSM Start State 0 1 lw or sw J R B 3 2 6 8 9 lw sw 4 5 7

7. Code • Initialize, set state = 0 • If state = 0 thenSet state 0 signalsSet state = 1 for next clock cycle • If state = 1 thenSet state 1 signalsSet state = 2 for next clock cycle • If state = 2, depending on opcode, we will either go down path of register-type, load word, store word, branch, or jump instruction.

8. Cycle Boundaries • Multiplexers are handled at the end of each cycle • Multiplexer outputs serve as “variables” to be used as inputs for the next clock cycle • Either a multiplexer or another stand-alone component must have a steady-state output to serve as input for the next cycle

9. Multicycle Datapath Shift left 2 25-0 25-21 28-31 20-16 Instr. reg. (IR) A Reg. PC Addr. 15-11 Memory ALU Register file ALUOut Reg. Data Mem. Data (MDR) B Reg. 1 Sign extend Shift left 2 0-15 Opcode 31-25

10. Completed !! • Any Question? Comments?