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KM3NeT CLBv2

KM3NeT CLBv2. PAR Error:. PAR ERROR:

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KM3NeT CLBv2

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  1. KM3NeT CLBv2

  2. PAR Error: • PAR ERROR: • ERROR:Place:1398 - A clock IOB / BUFGCTRL clock component pair have been found that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock IOB component <RESET> is placed at site <D11>. The corresponding BUFGCTRL component <ix18505z53357> is placed at site <BUFGCTRL_X0Y25>. The clock IO can use the fast path between the IOB and the Clock Buffer if the IOB is placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL sites in its half of the device (TOP or BOTTOM). You may want to analyzewhy this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucffile to override this clock rule. < NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE; >

  3. PAR Error: • Cause: RESET is connected to a “N” type Single Region Clock Capable (SRCC) pin. • As the design grows, one needs to use the top & bottom part of the FPGA. Only “P” side pins can drive global clock nets. • We already had this issue for CLK20_VCXO • see slide 14: • http://indico.cern.ch/event/286898/contribution/4/material/slides/0.pptx • Solution: Swap FPGA pins for NRESET and RESET (note: NRESET connects to “P”)

  4. LM32_2nd Memory: • Vincent ran into memory limitations • always the same story with these memory hungry software engineers… • Increased from 88 Kbytes to 128 Kbytes • BMM files for XST and Precision changed but nobody should have noticed this…

  5. UDP Length error: • With higher TDC rates in rare conditions… • Missing either 1, 2 or 3, 16-bit words randomly • Checksum: “unchecked, not all data available”

  6. UDP Length error: • Who is toblame? • TDC + StateMachine (unlikely) • It just forwards payloadthatwillbecountedby IPMUX • IPMUX (unlikely) • The correct length word (countedby IPMUX) is in the header so IPMUX must have seenall data words… • The interface between IPMUX and WR (maybe) • WR endpoint (maybe)

  7. Test to hunt for the UDP Length error: Test packet generator: 16 x okay • Added UDP Length checker. Verificationsignalling (toOscilloscope): • LengthOkay • Length Error 0 x error

  8. Test to hunt for the UDP Length error: Onlyokay’s Conclusion: Up to the WRPC input all is okay! Focus on WRPC (endpoint) 0 triggers on error

  9. Further points checked: • Input ep_tx_frames (= WR MAC) • Input 1000basex-PCS • Input PHY • All okay!? I must bedoingsomething wrong… • Sorry… Got the wrong file updated. • => work in progress.

  10. IPMUX arbitration • Whilehunting down the UDP Length error issue: • I had a simulationstall. • IPMUX connects to the non empty input fifo of the TDC channel and starts reading packet payload. It keeps connected (there is no other way) until it completes the payload transfer (i.e. EOD). When for some reason no EOD is generated (or it takes a while, i.e. one time slice) then it keeps waiting, effectively blocking other inputs. • Example case study: • Long time slice with no data IPMUX is connectedto TDC for the time slice duration • Duringthis time AES data shouldbebuffered

  11. IPMUX arbitration • Three parameters to optimize the dataflow: • Proper setting for the packet size. • Buffer sizes (either the TDC/AES fifos or the IPMUX input fifo) can help optimize the dataflow. • The arbitration scheme. Now all channels are served equally so one has to wait for the other. • For the time being I see no problems but we shouldbeaware of thisbehaviour!

  12. Empty Time Slice to DAQ? • Tommasoproposedto have no TDC-UDP data packetsifthere is no TDC data in the Time Slice. • Do we want thatbehaviour? • If we don’t send data each Time Slice (even if it is empty) then the DAQ cannot distinguish between data that is still in the pipeline or apparently the time slice was empty. => a timeout is needed. • Sendingan Time Slice packetthatcontains no TDC data at leasttells the DAQ thatitcan continue with data processing. No timeout.

  13. PRR • ½ DOM electronics + readout • EMC • Climate • Rate test • Golden image • Golden image reprogrammable itself? => Test! • SFP wave length shift • Test: unplug CLB Tx fiber and see if we can switch a LED on/off (i.e. without upstream communication)

  14. Other topics that keep me busy • Pause frame implementation • Gave some feedback toEmilio@ TIPP2014 • Feedback 7-Sols to WR community? • Calibration. Yes/no WR in the DOMs • WR veryhandyfor Dark Room Calibartion! • Alsohandyfor Dark Room Calibartion: Make PPS signalavailablewithan assembled DOM (RF? Via Nano-Beacon?) DU-Base Measure strings “constant” delays (tobeconsidered as delta Rxforeach of the DOMs) WR-Calibrator

  15. Backup slides

  16. Zoom into WRPC: Again: Onlyokay’s • Added UDP Lengthchecker. Verificationsignalling (toOscilloscope): • LengthOkay • Length Error 0 triggers on error

  17. Zoom into WRPC endpoint: ep_1000basex_pcs phy_tx pcs_fab txpcs_fab snk serdes_tx Ep_tx_framer Wr_gtx_phy_kintex7 ep_tx_pcs_16bit errors okay okay Again: Onlyokay’s 0 triggers on error

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