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KM3NeT CLBv2. UDP Length error:. With higher TDC rates in rare conditions… Bad Network Interface Card!. Top Level CLB design. SVN now accommodates KC705, CLBv2.1 and CLBv2.2 designs (via generics). SVN version 1023 CLBv2.2 “only” has 4 DIP switches so for uniformity all designs, DIP:
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UDP Length error: • With higher TDC rates in rare conditions… • Bad Network Interface Card!
Top Level CLB design • SVN now accommodates KC705, CLBv2.1 and CLBv2.2 designs (via generics). SVN version 1023 • CLBv2.2 “only” has 4 DIP switches so for uniformity all designs, DIP: • UDP Test Packet Generator IPMUX(2) • UDP Test Packet Generator IPMUX(3) • UDP Test Packet Generator IPMUX(2) continuously • IRQ0
CLBV2.2 • Sometimes USB port only shows one USB entry after power-up. Need to unplug and plug the USB connector to have both USB ports available.
Request from Optical Network(Gerard, Jan Willem) • Loopback • Implement PRBS (Generator and Checker) • Tx Enable • All default into the proper position after power-up and reset. • This involves: • adding some bits in register (MDIO MCR, part of WR “ep_pcs_tbi_mdio_wb.vhd”) => done! • adding functionality to WR-LM32 embedded software (plus interface to LM32_2nd) • Added bits in MDIO Control Register: • 24:22 = tx_prbs_sel(2:0) • 21 = sfp_tx_disable • 20 = sfp_los • 19 = sfptx fault • 18:16 = loopback (2:0) • Note that RX_PRBS_ERR_CNT is only accessible via the Dynamic Reconfiguration Port and therefore RXPRBSSEL, RXPRBSCNTRESET are not implemented.
XADC interface • XADC okay! • Note: freezer spray got the FPGA min temperature down to -22.91C
Unplug TX fiber(minic SFP laser off wavelength) • No matter if you unplug Tx or Rx fiber, the WR link goes down. • Probably due to WR Link State Machine • => study TX RX
Unplug TX fiber • Monitor Kintex7 PHY signals (wr_gtx_phy_kintex7.vhd): • txpll_lockdet => always ‘1’ • tx_rst_done => always ‘1’ • rxpll_lockdet=> pulse low 9 us when either Tx or Rx unplugged • rx_rst_done=> pulse low 9 us when either Tx or Rx unplugged • Pulse due to WR software that resets the PHY during initialization under control of the WR link startup state machine. • WR software needs revision! This is tricky since it will affect the reset and startup procedures of various functions (including locking of PLL’s etc.). • This task should be assigned manpower!
XST versus Precision • Synthesis result of the current sources differs. • XST okay • Precision fails • Different behavior for TDC and State Machine output data. • Cause… ? To be investigated!
Monitoring channel (proposal) stmachine (2) IPMUX TDC TDC Ch-0 Hits-0 Ch-1 AES Ch-2 Test Ch-3 Hits-30 Clr Set LM32 Busy LM32 DPRAM IRQ Latch on “timeslice_start” Clear on “timeslice_start” Start register transfer on “timeslice_start” timeslice_start • Monitoring each time slice: • A set of hardware writable registers (i.e. snapshot of the TDC hits counters) • A slice of DPRAM accessible for the LM32_2nd Currentlyconnectedto a dummy
Monitoring channel (proposal) • At the start of time slice “n”: • The state machine takes a snapshot of the TDC hit counters (freeing the counters for the current time slice ‘n’). The latched information are the hit counts for ‘n-1’. • The LM32_2nd software (IRQ routine) had time during time-slice ‘n-1’ to prepare monitoring data in DPRAM. • One (small) UDP packet can be assembled fast (one or two clock cycles per register or DPRAM access by stmachine channel 2) since all data to transfer is available. • An “busy” bit in a stmachine register which signals that the UDP packet assembly completed may be helpful (set with “timeslice_start”, clear after stmachine-2 transfer complete). The LM32_2nd can check this bit in its IRQ-routine to see if all data in the DPRAM section is transferred and the section is free for access of new values.
Documentation • Revision of TDR • Moved: • “KM3NeT_ELEC_WD_2013_009_CLBv2_Register_description_PJ_VvB_DC_VK_Draft.docx”fromGoogle Docs so it is no longer in the claws of Google who mutilates the document markup (the hell with Google Docs!) • Now Google Docs “KM3NeT_ELEC_WD_2013_009_CLBv2_Register_description_PJ_VvB_DC_VK_Draft.docx” only contains a link to the SVN document: https://isvn.ific.uv.es/repos/KM3NeT/CLBv2/trunk/fw/CLBv2_Design/clb/doc/KM3NeT_ELEC_WD_2013_009_CLBv2_Register_description_PJ_VvB_DC_VK_Draft.docx