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KM3NeT CLBv2

KM3NeT CLBv2. To do list:. Done: Add AES sources to top level schematic Newest sources from Antonio in place Inspect I2C timing issue with Octopus Done and understood (I2C abort command didn’t check for completion ) Add Multi boot sources to LM32_2 nd and test SPI Flash

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KM3NeT CLBv2

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  1. KM3NeT CLBv2

  2. To do list: • Done: • Add AES sources to top level schematic • Newest sources from Antonio in place • Inspect I2C timing issue with Octopus • Done and understood (I2C abort command didn’t check for completion) • Add Multi boot sources to LM32_2nd and test SPI Flash • Added (had issue with ICAPE2 optimization for Precision) • Currently: • Solve 4 ns issue • Solved but not completely understood… • Clock stability test (in cooperation with University of A’dam) • Get experience with measuring calibration parameters (in cooperation with Mar van der Hoek) • Ethernet flow control (PAUSE frames) discussion with 7-Solutions and Athenes.

  3. To do list: • Soon: • Add StMachine, TDC sources to top level schematic • Prepare for system test • EMI test • Shouldn’t the registers of ICAPE2 in multiboot be readable and writeable in a generic way (mapped on the wishbone bus)? This opens the possibility to use all: • Warm Boot Start Address (mboot) • Watchdog Timer • Boot History Status

  4. Clock stability tests (cooperate with UVA) 10 MHz reference PPS Other data generators Other data generators 200 mbps Measure long term stability PPS

  5. Actual asymmetry measurement using WR(measure unknown calibration parameters in cooperation with Mar van der Hoek)Measurement 1 t1 t2 DRXS DTXM • df1 • (= dMS+ dSM) t4 t3 DTXS DRXM • Round Trip Time (Rtt from WR GUI): • Rtt(f1) = D + df1

  6. Measurement 2 t1 t2 DRXS DTXM • df2 • (= dMS+ dSM) t4 t3 DTXS DRXM • Round Trip Time (Rtt from WR GUI): • Rtt(f1) = D + df2

  7. Measurement 3 t1 t2 DRXS DTXM • df1+ df2 t4 t3 DTXS DRXM • Round Trip Time (Rtt from WR GUI): • Rtt(f1) = D + df1 + df2 • 3 equations, 3 unknown => Now calculate: • D • df1 • df2

  8. Measurement 4 t1 t2 DRXS DTXM • df2 t4 t3 DTXS DRXM • Knowing D, df1 and df2, => calculate lSC delay

  9. Measurement 5 t1 t2 DRXS DTXM • df2 t4 t3 DTXS DRXM • Knowing D, df1 and df2, => calculate lDC delay • EDFA assymetry = lDC- lSC

  10. CLBv2 EMI • EMScan: • EHX-42 150kHz-4GHz EMC/EMI problems diagnostic tool • Ordered ½ March • Lead time 4-6 weeks • => Expected beginning of May

  11. Pause request • Discussionwith 7 Solutions(and Athens). • Pauseimplementation on layer-2 usingunicast MAC addressesinstead of multicast. • An important item thatpopped up: • A DOM thatrequestspausewill halt the broadcast link if PAUSE is implemented on layer-2 (MAC). • This is a “feature” thanksto the broadcast architecture. • DOM pauserequestshouldbemaskable.

  12. Backup slides

  13. Actual asymmetry measurement using WR(measure one of the unknown calibration parameters in cooperation with Mar van der Hoek) t1 t2 dMS DRXS DTXM Rtt t4 t3 dSM DTXS DRXM • Accumulated hardware delays • D=DTXM+DRXS+DTXS+DRXM • Accumulated fiber delays • d= dMS + dSM • Asymmetry set to 0 for the time being… • Trick: 3 Round Trip Time (Rtt from WR GUI) measurement, 2 fibers • Rtt(f1) = D + df1 • Rtt(f2) = D + df2 • Rtt(f1+f2) = D + df1+ df2

  14. Actual asymmetry measurement using WR(measure one of the unknown calibration parameters) KC705+SoftPLL KC705+SoftPLL t1 t2 DRXS DTXM t4 t3 DTXS DRXM WR slave WR master • Two measurements on the EDFAs in the node • Get hands-on experience KC705+SoftPLL KC705+SoftPLL t1 t2 DRXS DTXM t4 t3 DTXS DRXM WR slave WR master

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