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KM3NeT CLBv2. Peters to do list:. Currently: Solve 4 ns issue (seems to be a very tough one!) Add Multi boot sources to LM32_2 nd and test SPI Flash Soon: Add StMachine, TDC sources to top level schematic Add AES sources to top level schematic Inspect I2C timing issue with Octopus
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Peters to do list: • Currently: • Solve 4 ns issue (seems to be a very tough one!) • Add Multi boot sources to LM32_2nd and test SPI Flash • Soon: • Add StMachine, TDC sources to top level schematic • Add AES sources to top level schematic • Inspect I2C timing issue with Octopus • Clock stability test (in cooperation with University of A’dam) • Get experience with measuring calibration parameters (in cooperation with Mar van der Hoek) • Prepare for system test • EMI test
WR Switch:PPS Timing issue when sending bunches • This issue needs to be understood and sorted out! • Greg Daniluk (ep-tx_framer.vhd) PPS aligned (Okay) PPS Switch PPS CLBv2 In steps of 4 ns (@ 1 second pace) PPS rising edges get de-aligned Until -826 ns is reachedand in steps of 4 ns (@ 1 second pace) PPS risingedges get alignedagain
CLBv2 + Octopus + PMT-Base • Vincent tested I2C communication for each PMT-Base connector on Octopus large/small. • All okay! Although… • … a timing issue is yet to be understood! • Test done with 4 bases at a time, hence 4 ID’s and other channels I2c-error
Clock stability tests (cooperate with VU) 10 MHz reference PPS Other data generators Other data generators 200 mbps Measure long term stability 62.5 MHz PPS
Actual asymmetry measurement using WR(measure one of the unknown calibration parameters) KC705+SoftPLL KC705+SoftPLL t1 t2 DRXS DTXM t4 t3 DTXS DRXM WR slave WR master • Two measurements on the EDFAs in the node • Get hands-on experience KC705+SoftPLL KC705+SoftPLL t1 t2 DRXS DTXM t4 t3 DTXS DRXM WR slave WR master
CLBv2 EMI • EMScan: • EHX-42 150kHz-4GHz EMC/EMI problems diagnostic tool • Ordered ½ March • Lead time 4-6 weeks • => Expected beginning of May