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KM3NeT CLBv2

KM3NeT CLBv2. Implementation issues porting KC705 design to CLBv2 Proto. 20 MHz VCXO I2C tri-state pins PPS_P/N and FPGA_CLK_P/N LVDS_25 conflict FLASH_SPI_CCLK on C8 => For details: see “backup slides” Note that there is still one single design

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KM3NeT CLBv2

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  1. KM3NeT CLBv2

  2. Implementation issues porting KC705 design to CLBv2 Proto • 20 MHz VCXO • I2C tri-state pins • PPS_P/N and FPGA_CLK_P/N LVDS_25 conflict • FLASH_SPI_CCLK on C8 • => For details: see “backup slides” • Note that there is still one single design • Synthesis generics and UCF file determine the platform

  3. CLBv2 Proto(= same as KC705 + SoftPLL) 31 TDCs IP/UDP Packet Buffer Stream Selector (IPMUX) Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Fifo TDC 30 Rx Stream Select Rx_mac2buf Rx_mac2buf Rx_buf2data wrf_src wrf_snk Flags RxPort_m Management & Control S aux_master State Machine Management & Config. 6 1 7 Pause Frame 5 ADC 0 Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx Stream Select Tx_pkt2mac Tx_pkt2mac Tx_data2buf Multiboot 0 1 Flags 2 TxPort_m S Management & Control Nano Beacon S ext_wb M M M M S M M M M M Debug LEDs WB Crossbar (1x8) WB Crossbar (2x3) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C UART SPI Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS, 125 MHz) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

  4. CLBv2 Proto Results • Ping is operational: • see http://pi1222.physik.uni-erlangen.de/Electronics/26 • WR-timing: • WR Servo in state “track phase” • Calibration parameters can be stored: • I2C EEPROM and SFP are accessible • There is a clock issue: • No fixed latency between VCXO and serial Tx stream (GTX internal PLL; clk_gtx_i -> tx_out_clk_o phase jumps @ reset) • This was not an issue on the KC705 (I’ll check again!) • I’m starting to get worried a bit… => it needs further study. Note: Both LM32 CPUstobeoperational!

  5. CLBv2 Proto Power consumption and Resource usage • Ping design taken as a reference. • Adding the rest of the system adds resources and power. • The final dissipation and resource usage is only known after integration. • CLBv2 Proto “Ping” ~3.9 W (including debugging FMC@360 mW and 850 nm SFP@460 mW) • Resources: • Number of Slice Registers: 9,992 out of 202,800 4% • Number of RAMB36E1/FIFO36E1s: 71 out of 325 21% • Number of RAMB18E1/FIFO18E1s: 18 out of 650 2% • Number of BUFG/BUFGCTRLs: 5 out of 32 15% • Number of GTXE2_CHANNELs: 1 out of 8 12% • Number of IBUFDS_GTE2s: 1 out of 4 25% • Number of MMCME2_ADVs: 2 out of 8 25% • Tentative estimate: XC7K160T Speed grade 1 (slowest) does the job. • To figure out margin try a fit of the integrated design for a 140 MHz clock

  6. Other CLBv2 Proto issues • All listed in google document: • KM3NeT_ELEC_2014_001_Doc-Prototype_design_changes_ELEC_draft • Use proper tooling to assemble GBX connectors • http://pi1222.physik.uni-erlangen.de/Electronics/19 • Placement of the Nanobeacon connector (J22) • http://pi1222.physik.uni-erlangen.de/Electronics/21 • !!!Attention!!! The Power connector (J2) has a pin swap as compared to the CLBv1! • http://pi1222.physik.uni-erlangen.de/Electronics/22 • The FMC connector screws have a close encounter with components C128, C131, R88 and R89 • http://pi1222.physik.uni-erlangen.de/Electronics/23

  7. 16 ns phase jump study (seen on KC705) • Last meeting reported a 16 ns phase jump • This appears to be a non-issue: • Due to the PHY TxOutClk and RxOutClk not being locked when connected to a Linux machine. • In that case the SoftPLL is not locked so the RxOutClk is related to the Linux Machine and TxOutClk is our (free running) VCXO.

  8. Calibration • Extensive email contact with Greg Daniluk and Javier Serrano. • “Relative” versus “Absolute” calibration • WR calibration document describes “relative” calibration, i.e. with respect to a WR device that is elected to be “THE” calibrator. • Relative calibration is an “easy” procedure but, … • … Calibrated WR devices that are calibrated with different WR-calibrators will not provide exact timing. • With respect to standardization “absolute” calibration would be better! • It is more reliable over time • all WR devices can be exchanged (different vendors, globally). • … but it is more difficult to achieve.

  9. Calibration • We learn a lot about the calibration issues! • The calibration job is done when using a “KM3NeT” WR-calibrator (i.e. use relative calibration) • This needs to be a single golden KM3NeT WR device to be used over the lifetime of the detector… • We plan to do more study with respect to “absolute” calibration. • More reliable over time and exchangeable with other WR gear globally.

  10. WR PTP Core • New release (version 2.1) • http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_release-v21 • Our input is not yet integrated • Currently being processed by Greg Daniluk: • git branch “stuff_from_peter” • => Keep our files for the moment and wait for Greg to merge our input in the git master.

  11. Workshop 28-30 January • “Critical Design Review”? • Are we already able to review the design? • Suggestion: Lets have a workshop and start to work with the people involved on the integration of the CLBv2 firmware.

  12. Status Listing • Currently: • KC705 -> CLBv2 Proto porting • Calibration • To do list (in order of priority): • Study: Reset button puts the system in a weird state • Implement Rx Pause frames • Wish list: • LM32 debugger

  13. Backup SlidesMore details…

  14. Implementation issues on CLBv2 Proto • 20 MHz VCXO • KC705 design uses an IBUFGDS • CLBv2 uses IBUF • Due to the issue were the single ended 20 MHz VCXO signal was routed to a “negative” defined FPGA input pin. • Issue solved on CLBv2 • I2C tri-state pins • KC705 + SoftPLL: pins must be driven ‘Z’ • CLBv2 pins no longer exist • Issues solved by entity KC705_Support and generic g_use_clbv2 (default true)

  15. Implementation issues on CLBv2 Proto • PPS_P/N and FPGA_CLK_P/N are LVDS • LVDS_25 conflicts with VCCO3.3 on BANK 116 • Note that FPGA_CLK_P/N is an input in the current design… • Issues solved by generic g_use_clbv2_proto selecting either: • OneOBUFDS (differencial output) • Twocomplementairy driven OBUF (single ended output) mimicing a differencial signal • This signal needs to be solved on future PCBs for the next series.

  16. Implementation issues on CLBv2 Proto • FLASH_SPI_CCLK on C8 • C8 is a dedicated configuration pin… • Diego => “use the primitive STARTUPE2”

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