Performed by: Michael Ginzburg Klement Sagi Instructor: Alex Gurovich

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט (חלק א’/סופי) Subject: הקמת Embedded system על בסיס כרטיס PROC20K-1 של חברת גידעל ומעבד NIOS של חברת Altera Performed by: Michael Ginzburg Klement Sagi Instructor: Alex Gurovich סמסטר חורף שנה תשס"א 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract The biggest advantage in the world is to make large designs easily debugging and quickly testing. PROC20K-1 card of Gidel company with FPGA chip give an answer for this advantage. Another question on this days is how to give a user opportunities to change hardware configuration. Altera Nios Embedded Processor is a fully programmable solution and decision for many problems. This project integrates both designs in one system with a number of fetchers. This system could be a good bases for continue projects. 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description Nios embedded processor and on-chip RAM are integrated to FPGA chip on PROC20K board. The board is connected to PCI bus. Local bus is an interface between PCI bus and the design. ProcWizard software application controls the design. 3

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specification • Hardware PROC20K-1 card of Gidel company NIOS Embedded Processor of Altera company • Software ProcWizard Quartus (TM) II Leonardo GNUPro for NIOS 4

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram Local Bus RAM 1 RAM 2 NIOS Embedded Processor 5

6. Data Data Write Address Read Address Write enable RAM 1 RAM 2 Read Address Data from CPU Write Address Data to CPU Write enable NIOS CPU Memory mapped periphery 1 Memory mapped periphery 2 ROM High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram 6

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Software example RAM1 CPU RAM2 A + C D B *

8. Lclk Reset_n Addres_to_the_mm_perf1 Data_to_cpu_to_the_mm_perf1 Select_to_the_mm_perf1 Cpu_write_n_to_the_mm_perf1 Cpu_read_to_the_mm_perf1 High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Memory-Mapped Peripheral Reading Cycle

9. Lclk Reset_n Addres_to_the_mm_perf2 Data_from_cpu_to_the_mm_perf2 Select_to_the_mm_perf2 Cpu_write_n_to_the_mm_perf2 Cpu_read_to_the_mm_perf2 High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Memory-Mapped Peripheral Writing Cycle