Performed by: Alexander Pavlov David Domb Instructor: Mony Orbach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט (סופי) Subject: GPS/INS Computing System Performed by: Alexander Pavlov David Domb Instructor: Mony Orbach סמסטר אביב 2009 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract • Developed in the “Technion” and Implements the tightly coupled INS/GPS navigation unit, with the particle filter. • The algorithm stages: 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Solution – top design 3

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Basic Architecture Finished Start Basic Streaming Block Control Write request Full Data in InputPath Empty Read Request Data out OutputPath • 24Bit words data bus. • FIFO-Like streaming interfaces ( Request + Empty / Full ) • Controlled By Start/Finished activation mechanism 4

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Particle Propagation Unit Particle Propagation Unit clock finish reset start X[0..439] X_OUT[0..439] INS[0..287] 5

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Particle Propagation Unit Propagation Unit 1 MUX (6 to 1) Propagation Unit 2 Propagation timing control Propagation Unit 6 6

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Single Particle Propagation Data Flow Propagation flow control 7

8. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Estimation Unit Estimation Unit clock Estimation_Ready reset New_Data_In X[0..439] ESTIMATED_DATA [0..439] W[0..23] 8

9. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Estimation Unit × X Σ Estimated Data W 9

10. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Physical Implementation • Physical implementation of entire design was unsuccessful due to lack of FPGA resources. • Therefore, only 1 of the 6 parallel “propagation unit” blocks was implemented. • A design with 6 prop units will need approximately: • 130K combinational ALUTs (85K available). • 162K logic registers (85.2K available). • 20M block memory bits (8.25M available). • 4074 DSP blocks (896 available). 10

11. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Timing Analysis • The implemented design of 1 prop unit produced: • Particle LATENCY – 97 clock cycles (from “start” to “finish”) @100MHz = 1uSec • Throughput of 38 clock cycles (from “finish” to “finish”) @100MHz = 380nSec • The total time with the implemented design of 1 prop unit produced was 30,000 particles in 1,140,059 100MHz clocks = 11.4mSec. 11

12. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Accuracy Analysis • We have encountered many problems while trying to test our results: • The “Generic program” for 1 FPGA did not work correctly – we were unable to control the inputs to the design. • The “Generic program” for 4 FPGAs did not work as anticipated with the SW data files: • The SW data input files were arranged not according to the “bits order” agreed upon. • The program’s data output files did not reflect the output values from our design correctly. • We have made a manual accuracy check for one particle, by comparing the result as viewed with the “signal tap” tool to the SW result. • For the tested particle, we got a location result which was different from the SW result by 0.0002% 12

13. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project Summary • Implementation of our design - PARTIAL - due to lack of FPGA resources. • Design testing and integration - PARTIAL - due to problems with the testing environments and no cooperation from other design teams (which finished their project). • In terms of possibility – it seems that it is possible to implement the “Propagation” and “Estimation” stages of the project, within the necessary timing requirements, on a better, more powerful FPGA (without changing the design) 13