Performed by: Oron Port Instructor: Mony Orbach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project Final Presentation Subject: Jitter Generator Performed by: Oron Port Instructor: Mony Orbach Winter 2006/7

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project Definition • Extension of the project “Jitter experiment”, performed by Gregory Zabolotov during Spring 2005 semester. • Developing GUI-based software for an easy user control of a deterministic, periodic Jitter applied on a fed clock.

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות What is Jitter? Jitter is the short term variation of the significant instants of a digital signal from their ideal positions in time.

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Types of Jitter

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Why do we need a Jitter Generator? • Ability to test our system’s robustness against anticipated / approximated parasitic Jitter signal in a controlled environment: • See how different Jitter signals effect our system. • Anticipate a problem due to Jitter interference, and verify a solution works before the entire system is completely integrated. • Ability to experiment in laboratory conditions.

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Existing Hardware & Software Extension slot PDC Jitter Generator (JG) PCB Memec 456 virtex II Pro board Hardware: developed for the Memec 456 virtex II Pro board’s extension slot. Using a Programmable Delay Chip (PDC), it is possible to define a delay between 2.2nsec and 12.2nsec (in 10psec increments) for a given clock signal. Changing the delay continuously (@50MHz) and periodically creates a deterministic periodic jitter effect. The JG board is connected to the SOPC’s Plb bus. The interface between the bram and the JG board was built. Jitter-Cycle period: 8*1024/50M=163.84usec (6104Hz) Software: Basic program (on the SOPC) which reads a requested (via RS-232) jitter amplitude (in nsec) and frequency and loads the bram memory accordingly.

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project Implementation 3 1 2 Jitter Gen. Virtex II PRO RS-232 E x t e n s i o n s l o t Data Bus Memec 456 Board Interface #1: MMI – Man-Machine-Interface GUI – Graphical-User-Interface 1 Interface #2: RS-232 communication Transferring a jitter period’s data selected in interface #1 to the SOPC’s bram memory, and other commands according to what was selected (start BERT, etc…) 2 Interface #3: Virtex II Pro’s Plb Updating the PDC on the JG board with the current delay time, according the tables filled in the SOPC’s bram memory during interface #2. Interface already existed in prev. project. 3

8. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Features • Easy to use and intuitive GUI. • Inject known periodic jitter on any SMA-fed clock of up to 4GB (ECL differential voltage level). • Wide variety of signal selection (sine, square, triangular, sawtooth). • Customize jitter using drawing tool. • Fast Jitter signal loading (~3 secs). • Interfacing with Matlab, and basically any DDE client-enabled application. • Allow Rocket IO clock generation + BER test.

9. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Platform • Development: • Windows XP + Visual Studio .NET 2003 • EDK 7.1 + Memec 456 Board + Virtex II Pro FPGA • Runtime: • Windows XP + .NET 2.0 Framework • Memec 456 + Virtex II Pro FPGA

10. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Breakdown

11. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Matlab-Jitter Gen GUI Interface (DDE client/server) • DDE (Data Dynamic Exchange) is a method of transferring data between application under windows. • Matlab, Excel and many other application support DDE. • The GUI Jitter Gen application implements a DDE server, while Matlab acts as a DDE client- sending commands and data. • Alternatives to DDE: • COM/OLE – Difficult to implement, both as client and server. • Communicating through files/windows messages- clumsy and slow.

12. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Jitter Gen GUI-Power PC Interface(Communication via UART) • Parameters: Baud rate: 115200bps, Parity: N, Data bits: 8, Stop bit: 1, No handshaking • Protocol: Packets of 2 bytes each. Empty packet for byte-sync.

13. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות

14. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Jitter Gen GUI-Power PC Interface(Communication via UART)

15. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Testing the system… • Connecting a Windows XP PC to the Memec 456 board via crossed RS-232 cable (RxTx). • Clock generated using BERT tool to configure the Rocket I/O. • Input the clock to the PDC Board via SMA connectors. • Connect the PDC Board’s HI clock signal to a Real-Time Scope (7G samples/sec), which includes a Jitter analysis software component. • Jitter signal is viewable via TIE (Time Interval Error) display. • Comparing both generated and actual Jitter signals, shows the system is functioning as anticipated. • System integration completed successfully!

16. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Sine wave @ 305kHz, 200ps peak

17. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Sine wave @ 305kHz, 200ps peak

18. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות 2

19. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Testing the system… 2

20. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Testing the system… 2

21. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Testing the system… 2

22. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Custom Jitter Signal

23. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Testing the system… 2

24. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות 3 Sine waves @ 76k, 305k, 1.22M [Hz](Matlab Example) Data_length=8192; A=100; F=76294; Offset = 2850; tau=2e-8; phi=0; dde_handler=ddeinit('JGen','INIT'); v=[0:(Data_length-1)]; v1=A*sin(2*pi*(F*v*tau-phi)); v2=A*2*sin(2*pi*(F*4*v*tau-phi)); v3=A*3*sin(2*pi*(F*16*v*tau-phi)); v=floor(v1+v2+v3+Offset); ddepoke(dde_handler,'DATA_XFER',v); ddeexec(dde_handler,'SHOW') ddeterm(dde_handler);

25. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות 3 Sine waves @ 76k, 305k, 1.22M [Hz]

26. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Breakdown 2

27. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Breakdown 2

28. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Problems and Limitations (1) • Design is built for Memec 456 Virtex II Pro & EDK 7.1, and will NOT work on a different platform without modifications. • Only H/W (CPU) reset enables loading a new Jitter signal (a bit inconvenience to the user). • Jitter signal cycle is fixed and cannot be changed, thus limiting potential fully-periodic Jitter signals to multiplications of a Jitter cycle (6104 Hz).

29. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Problems and Limitations (2) • High-peaked Jitter signals weren’t measurable using the mentioned jitter analyzer. • Possible parasitic Jitter in Rocket IO clock (550KHz periodic jitter).

31. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Conclusions (1) • Possible improvements in design: • Jitter cycle size configurable via software. • FPGA hardware enhancement to support Random jitter simulation mode. • Create a more generic design (to support more/newer platforms).

32. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Conclusions (2) • Combining C++ Managed, C++, and C was problematic and not recommended (was necessary due to DDE implementation) for future projects. • Equipment availability caused delays: • Memec 456 board sharing. • Verification equipment required for full system integration & testing (Real-Time scope + Jitter analyzer).

33. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Conclusions (3) • Separate Hardware & Software designs managed to fully integrate together. • Altogether, a fun project! Was nice to see the system fully working.

34. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Thanks • This work wouldn’t have been possible if it weren’t for the kind help and guidance from the following people: • Orbach Mony • Shoshan Eli • Rivkin Ina • Bekker Alexander • Framovich Dimitry • Zabolotov Gregory And thank you for listening…