Performed by: Roi Sherman Eyal Wilamowski Instructor: Mr. Michael Itzkovich

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט (חלק א’) Subject: Generic Daughter Board For 5510 EVM Performed by:Roi Sherman Eyal Wilamowski Instructor: Mr. Michael Itzkovich סמסטר חורף תשס"ב

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract The project aim is to implement a general purpose daughter board for the TI 5510 EVM prototype board. The card could be used for connecting of up to 4 DSP’s through the McBSP for Parallel Computation and system resources sharing. The card would have the ability to operate as master in a standalone mode, or even connect to an expansion board of it’s own. The implemented card is generic as possible yielding maximum use of pins, connectors etc. High percent of all resources are not purpose and controlled by the main control unit.

3. 2MB SRAM 1MB Flash EMIF Peripheral Interface MB Interface RS232 Control Unit (Altera) GPIO McBSP High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description • 3.3v operation for all components • 5v power supply • 8MBytes Address Space • 32 Bit Data Bus • FPGA Control Unit • JTAG programming interface

4. 2MB SRAM 1MB Flash EMIF Peripheral Interface MB Interface RS232 Control Unit (Altera) GPIO McBSP High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description (cont.) • General Purpose discrete interface • 1MB Flash Memory • 2MB Asynchronous SRAM • 2 x RS232 serial channels • 3 x McBSP channels • Led Indicators

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Hardware Specification • Altera’s EPF10K100ARC-1 FPGA • Altera’s EPC2TC32 • 2 x AMD 4Mb Flash MemoryAM29LV400BT-70 • 4 x Alliance 4Mb Async SRAMAS7C34098-10TC • 16-Bit Bus TransceiversSN74LVTH16245 • National’s LM1085 Voltage Regulator • 2 x RS-232 MAX3238 Transceivers

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Hardware Specification (cont.) • 2 x TL16C550CPT Single UART with FIFO • SN74LVC08A AND gates • MAX821TUS-T Voltage Monitor • 40MHz Oscillator • 1.8432MHz Oscillator

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Flash Memory MAIN PROPERTIES EVM 5510 4Mb Flash 4Mb Flash • 2 X 4Mb AMD Flash memory. • IC Arrangement 16*256M . DB Control • PN: AM29LV400-70. Package TSOP 48 pin . Data Address • Could be replaced by larger sized ICs with same pinout. Up to total of 4MBytes. MB Control • Conclusion: Fast , Reliable Manufacturer, Upgradeable. Control Unit (Altera)

8. FLASH High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות

9. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות SRAM MAIN PROPERTIES 4Mb Flash EVM 5510 4Mb SRAM 4Mb SRAM • 4 X 4Mb Alliance Semiconductor Async SRAM. 4Mb SRAM • IC Arrangement 16*256M . DB Control • 10nSec Access Time. Data • CS for each IC controlled by FPGA only. Address MB Control • Why asynchronous ? TI’s daughter board specification. Control Unit (Altera) • Conclusion: Large, Fast, available.

10. SRAM High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות

11. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות RS232 Channels MAIN PROPERTIES Control Unit (Altera) • 2 configurable standard RS232 serial channels. data data addr Ctrl addr Ctrl • TI TL16C550CPT single UART’s with 16 Byte FIFO. UART UART • MAX3238 RS232 Transceivers. • Standard DB9 connectors. RS232 Transceiver RS232 Transceiver • 1.8432Mhz Oscillator. • Memory Mapped. • Asynchronous operation, using interrupts. DB9 DB9

12. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות RS232 Channels (cont.) Control Unit (Altera) data data addr Ctrl addr Ctrl • Conclusion: • Industry standard UART. • Reliable & Available Transceiver. • Standard RS232 Connectors. UART UART RS232 Transceiver RS232 Transceiver • UART: IC or ALTERA CORE ? • Reduce FPGA resources. • Academic - more HW substance. DB9 DB9

13. UART CS PUPs RS232 TRANSCEIVER UART CLK 1.8432MHz High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות

14. Control Unit (Altera) Header 10 X 2 Header 10 X 2 Header 10 X 2 High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות GPIO MAIN PROPERTIES • 3 X 16 bit wide buses. • 10 X 2 connectors. Suitable for logic analyzer 100KΩ Termination Adapter. • Busses are buffered for FPGA protection & for Current driving. • Bi-directional TI’s SN74LVTH16245 bus transceivers (Standard & Availability). • Transceivers direction controlled by FPGA. • 40MHz/1.8432MHz clock signals. • UART data bus connected to a gpio bus. • 1 bus could be realized as open/gnd or open/vcc.

15. BUFFERS High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות

16. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות McBSP MAIN PROPERTIES EVM 5510 Control Unit (Altera) • 3 McBSP channels • Full duplex serial communication. • Double buffered. • Channel 2 is connected to the FPGA through spare pines in the McBSP connector. • Use of Channel 2 requires alteration of the MB. Header 4 X 2 Header 4 X 2 Header 4 X 2 • Main purpose – connecting DSP’s for parallel operation.

17. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA • Altera’s EPF10K100ARC-1 FPGA. • RQFP 240 pin package. • 189 IO pins, all used. • Size 1,200,000 bits. • Programmed by EPC2 E2PROM. • EPC2TC32 size : 1,695,680 bits. • JTAG interface for EPC2 programming.

18. ALTERA EPF10K100ARC LEDS CLK 1.8432MHz EPC2 High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות

19. Main Control High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram Memory Interface UART Interface addr addr data data ctrl ctrl Spare MB Signals Interface GPIO Interface ctrl Indicators Interface

20. 5v External Power Supply Reverse Power protect Power Regulator 3.3v Layer 6A Trace 4 pin standard PS connector Power Indicator OVP High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Power Supply

21. Set Delay To FPGA MAX821 Voltage Monitor MB Reset Manual Reset High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Reset Active Low Reset

22. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Design Issues • Timing: • DB System Clock 40MHz. • MB Supplies configurable Clock 20MHz ÷ 160MHz. • DSP  DB CS Delay ~23nSec (before simulation). • DSP  DB Memory Addr/Data ~9nSec • Fanout : • Borderline (capacity) for most memory signals. Single Buffer drives 7 outputs.

23. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Layout Guidelines • Place Memory IC close to Memory connector • Information Flow • Altera’s Pins same as connected IC’s pins as possible • Lines as simple as possible • Critical lines : Clocks • Easy Access to Connectors/Switch/Leds By The Numbers: Size: 191mm X 76.2mm 6 Layers 430 Nets ~1200 Pads

24. Power Connector EMIF Connector RESET FLASH Reverse S R A M OVP REGULATOR JTAG Header UARTS BUFFERS RS232 FPGA EPC2 BUFFER McBSP Headers Peripheral Connector High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Layout Flash

25. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות On The Agenda • Final Preparation for production. • Finish FPGA Code & Simulation. • Learning the Code Composer environment. • Writing test programs. • Electrical wiring test of the board after production. • Components assembly & Functional Debug. • Parallel Operation of 3 DSP’s.

26. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות The End