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This lecture covers the Ebers-Moll model, Gummel-Poon static npn circuit model, BJT characterization, and MOS capacitor and MOSFET characterization. It also includes parameter extraction techniques for various model equations and sensitivities.
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Semiconductor Device Modeling and CharacterizationEE5342, Lecture 27 -Sp 2002 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/
aFIF aRIR JCAC = IC -JEAE = IE E C B Ebers-Moll Model(No G-R curr) (Fig. 9.30 Semiconductor Physics & Devices, by Neamen, Irwin, Chicago, 1997, * throughout)
Charge componentsin the BJT From Getreau, Modeling the Bipolar Transistor, Tektronix, Inc.
Gummel-Poon Staticnpn Circuit Model C RC Intrinsic Transistor IBR B RBB ILC ICC-IEC= IS(exp(vBE/NFVt) - exp(vBC/NRVt)/QB B’ IBF ILE RE E
IBF = IS expf(vBE/NFVt)/BF ILE = ISE expf(vBE/NEVt) IBR = IS expf(vBC/NRVt)/BR ILC = ISC expf(vBC/NCVt) ICC -IEC = IS(exp(vBE/NFVt - exp(vBC/NRVt)/QB QB= {+ [+ (BFIBF/IKF + BRIBR/IKR)]1/2} (1 - vBC/VAF - vBE/VAR )-1 Gummel Poon npnModel Equations
VAF ParameterExtraction (fEarly) Forward Active Operation iC = ICC= (IS/QB)exp(vBE/NFVt), where ICE= 0, and QB-1= (1-vBC/VAF-vBE/VAR )* {IKF terms}-1, so since vBC = vBE - vCE, VAF = iC/[iC/vBC]vBE iC iB vCE vBE 0.2 < vCE < 5.0 0.7 < vBE < 0.9
Reverse Active Operation iE iB vEC vBC 0.2 < vEC < 5.0 0.7 < vBC < 0.9 VAR ParameterExtraction (rEarly) iE = -IEC= (IS/QB)exp(vBC/NRVt), where ICC= 0, and QB-1= (1-vBC/VAF-vBE/VAR ) {IKR terms}-1, so since vBE = vBC - vEC, VAR = iE/[iE/vBE]vBC
iC RC vBC - iB + + RB vBE - vBEx RE BJT CharacterizationForward Gummel vBCx= 0 = vBC+ iBRB- iCRC vBEx = vBE+iBRB+(iB+iC)RE iB = IBF + ILE = ISexp(vBE/NFVt)/BF + ISEexpf(vBE/NEVt) iC = bFIBF/QB = ISexp(vBE/NFVt) (1-vBC/VAF-vBE/VAR ) {IKF terms}-1
Definitions ofNeff and ISeff • In a region where iC or iB is approxi-mately a single exponential term, then iC or iB ~ ISeffexp (vBEext /(NFeffVt) where Neff={dvBEext/d[ln(i)]}/Vt, and ISeff = exp[ln(i) - vBEext/(NeffVt)]
Forward GummelData Sensitivities a Region a - IKFIS, RB, RE, NF, VAR Region b - IS, NF, VAR, RB, RE Region c - IS/BF, NF, RB, RE Region d - IS/BF, NF Region e - ISE, NE vBCx = 0 c iC b d iB e iC(A),iB(A) vs. vBE(V)
Simple extractionof IS, ISE from data Data set used • IS = 10f • ISE = 10E-14 Flat ISeff for iC data = 9.99E-15 for 0.230 < vD < 0.255 Max ISeff value for iB data is 8.94E-14 for vD = 0.180 iC data iB data ISeff vs. vBEext
Simple extraction of NF, NE from fg data iB data Data set used NF=1 NE=2 Flat Neff region from iC data = 1.00 for 0.195 < vD < 0.390 Max Neff value from iB data is 1.881 for 0.180 < vD < 0.181 iC data NEeff vs. vBEext
Simple extractionof BF from data • Data set used BF = 100 • Extraction gives max iC/iB = 92 for 0.50 V < vD < 0.51 V 2.42A< iD < 3.53A • Minimum value of Neff =1 for slightly lower vD and iD iC/iB vs. iC
RC vBCx vBC - iB + + RB vBE - RE iE BJT CharacterizationReverse Gummel vBEx= 0 = vBE+ iBRB- iERE vBCx = vBC+iBRB+(iB+iE)RC iB = IBR + ILC = (IS/BR)expf(vBC/NRVt) + ISCexpf(vBC/NCVt) iE = bRIBR/QB = ISexpf(vBC/NRVt) (1-vBC/VAF-vBE/VAR ) {IKR terms}-1
Sample rg data forparameter extraction • IS=10f • Nr=1 • Br=2 • Isc=10p • Nc=2 • Ikr=.1m • Vaf=100 • Rc=5 • Rb=100 iB data iE data iE, iB vs. vBCext
Simple extractionof BR from data • Data set used Br = 2 • Extraction gives max iE/iB = 1.7 for 0.48 V < vBC < 0.55V 1.13A< iE < 14.4A • Minimum value of Neff =1 for same range iE/iB vs. iE
Simple extractionof IS, ISC from data Data set used • IS = 10fA • ISC = 10pA Min ISeff for iE data = 9.96E-15 for vBC = 0.200 Max ISeff value for iB data is 8.44E-12 for vBC = 0.200 iB data iE data ISeff vs. vBCext
Simple extraction of NR, NC from rg data Data set used Nr = 1 Nc = 2 Flat Neff region from iE data = 1.00 for 0.195 < vBC < 0.375 Max Neff value from iB data is 1.914 for 0.195 < vBC < 0.205 iB data iE data NEeff vs. vBCext
Fully biased n-MOScapacitor VG Channel if VG > VT VS VD EOx,x> 0 e- e- e- e- e- e- n+ n+ p-substrate Vsub=VB Depl Reg Acceptors y 0 L
Flat band with oxidecharge (approx. scale) Al SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) Ex q(fm-cox) Eg,ox~8eV Ec EFm EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev
Q’d,max and xd,max forbiased MOS capacitor Fig 8.11** |Q’d,max|/q (cm-2) xd,max (microns)
I-V relation for n-MOS (ohmic reg) ohmic ID non-physical ID,sat saturated VDS VDS,sat
Universal draincharacteristic ID VGS=VT+3V 9ID1 ohmic saturated, VDS>VGS-VT VGS=VT+2V 4ID1 VGS=VT+1V ID1 VDS
Characterizing then-ch MOSFET VD ID D G B S VGS VT
Body effect data Fig 9.9**
SPICE mosfet model levels • Level 1 is the Schichman-Hodges model • Level 2 is a geometry-based, analytical model • Level 3 is a semi-empirical, short-channel model • Level 4 is the BSIM1 model • Level 5 is the BSIM2 model, etc.
Level 1 Static Const.For Device Equations Vfb = -TPG*EG/2 -Vt*ln(NSUB/ni) - q*NSS*TOX/eOx VTO = as given, or = Vfb + PHI + GAMMA*sqrt(PHI) KP = as given, or = UO*eOx/TOX CAPS are spice pars., technological constants are lower case
Level 1 Static Const.For Device Equations b = KP*[W/(L-2*LD)] = 2*K, K not spice GAMMA = as given, or = TOX*sqrt(2*eSi*q*NSUB)/eOx 2*phiP = PHI = as given, or = 2*Vt*ln(NSUB/ni) ISD = as given, or = JS*AD ISS = as given, or = JS*AS
Level 1 Static Device Equations vgs < VTH, ids = 0 VTH < vds + VTH < vgs, id = KP*[W/(L-2*LD)]*[vgs-VTH-vds/2] *vds*(1 + LAMBDA*vds) VTH < vgs < vds + VTH, id = KP*[W/(L-2*LD)]*(vgs - VTH)^2 *(1 + LAMBDA*vds)
Level 2 StaticDevice Equations Accounts for variation of channel potential for 0 < y < L For vds < vds,sat = vgs - Vfb - PHI + g2*[1-sqrt(1+2(vgs-Vfb-vbs)/g2] id,ohmic = [b/(1-LAMBDA*vds)] *[vgs - Vfb - PHI - vds/2]*vds -2g[vds+PHI-vbs)1.5-(PHI-vbs)1.5]/3
Level 2 StaticDevice Eqs. (cont.) For vds > vds,sat id = id,sat/(1-LAMBDA*vds) where id,sat = id,ohmic(vds,sat)
Level 2 StaticDevice Eqs. (cont.) Mobility variation KP’ = KP*[(esi/eox)*UCRIT*TOX /(vgs-VTH-UTRA*vds)]UEXP This replaces KP in all other formulae.
References • CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995. • M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993. • M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986. • Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997