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Semiconductor Device Modeling and Characterization EE5342, Lecture 20 -Sp 2002. Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/. Equivalent circuit above OSI. Depl depth given by the maximum depl = x d,max = [2 e Si |2 f p |/(qN a )] 1/2
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Semiconductor Device Modeling and CharacterizationEE5342, Lecture 20 -Sp 2002 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/
Equivalent circuitabove OSI • Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2 • Depl cap, C’d,min = eSi/xd,max • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’d,min
n-substr accumulation (p-channel) Fig 10.7a*
n-substrate depletion(p-channel) Fig 10.7b*
n-substrate inversion(p-channel) Fig 10.7*
Ideal 2-terminalMOS capacitor/diode conducting gate, area = LW Vgate=VG -xox SiO2 0 y 0 L silicon substrate tsub Vsub=VB x
Band models (approx. scale) metal silicon dioxide p-type s/c Eo Eo qcox ~ 0.95 eV Eo qcSi= 4.0eV qfm= 4.28 eV for Al Ec qfs,p Eg,ox ~ 8 eV Ec EFm EFi EFp Ev Ev
Flat band with oxidecharge (approx. scale) Al SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) Ex q(fm-cox) Eg,ox~8eV Ec EFm EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev
Experimental valuesfor fms Fig 10.15*
Fully biased n-MOScapacitor VG Channel if VG > VT VS VD EOx,x> 0 e- e- e- e- e- e- n+ n+ p-substrate Vsub=VB Depl Reg Acceptors y 0 L
Computing theD.R. width at O.S.I. Ex Emax x
Fully biased MOScapacitor in inversion VG>VT Channel VS=VC VD=VC EOx,x> 0 e- e- e- e- e- e- n+ n+ p-substrate Vsub=VB Depl Reg Acceptors y 0 L
Flat band with oxidecharge (approx. scale) Al SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) Ex q(fm-cox) Eg,ox~8eV Ec EFm EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev
MOS energy bands atSi surface for n-channel Fig 8.10**
References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986