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Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011

Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011. Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/. The npn Gummel-Poon Static Model. C. R C. I CC - I EC = IS ( exp(v BE /NFV t - exp(v BC /NRV t )/Q B. I BR. B. R BB. I LC.

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Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011

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  1. Semiconductor Device Modeling and Characterization – EE5342 Lecture 34 – Spring 2011 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc/

  2. The npn Gummel-Poon Static Model C RC ICC -IEC = IS(exp(vBE/NFVt - exp(vBC/NRVt)/QB IBR B RBB ILC B’ IBF ILE RE E

  3. IBF = ISexpf(vBE/NFVt)/BF ILE = ISEexpf(vBE/NEVt) IBR = ISexpf(vBC/NRVt)/BR ILC = ISCexpf(vBC/NCVt) QB = (1 + vBC/VAF + vBE/VAR ) {½ + [¼ + (BFIBF/IKF + BRIBR/IKR)]1/2 } Gummel Poon npnModel Equations

  4. Values for fmswith metal gate

  5. Values for fmswith silicon gate

  6. fms (V) Fig 10.15* NB (cm-3) Typical fms values

  7. Flat band with oxidecharge (approx. scale) Al SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) Ex q(fm-cox) Eg,ox~8eV Ec EFm EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev

  8. Flat-band parametersfor n-channel (p-subst)

  9. Flat-band parametersfor p-channel (n-subst)

  10. Inversion for p-SiVgate>VTh>VFB Vgate> VFB EOx,x> 0 e- e- e- e- e- Acceptors Depl Reg Vsub = 0

  11. Approximation concept“Onset of Strong Inv” • OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG= VTh • Assume ns = 0 for VG< VTh • Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh • Cd,min = eSi/xd,max for VG > VTh • Assume ns > 0 for VG > VTh

  12. Fig 10.9* qfp 2q|fp| xd,max MOS Bands at OSIp-substr = n-channel

  13. Computing the D.R. W and Q at O.S.I. Ex Emax x

  14. Calculation of thethreshold cond, VT

  15. Equations forVT calculation

  16. Fully biased n-MOScapacitor VG Channel if VG > VT VS VD EOx,x> 0 e- e- e- e- e- e- n+ n+ p-substrate Vsub=VB Depl Reg Acceptors y 0 L

  17. MOS energy bands atSi surface for n-channel Fig 8.10**

  18. Ex Emax x Computing the D.R. W and Q at O.S.I.

  19. Q’d,max and xd,max forbiased MOS capacitor Fig 8.11** xd,max (mm)

  20. Fully biased n-channel VT calc

  21. n-channel VT forVC = VB = 0 Fig 10.20*

  22. References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986

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