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Briefing: Independent NASA Test of RTSX-SU FPGAs Comparison of A54SX-A/UMC and RTSX-SU Differences. Rich Katz, Grunt Engineer NASA Office of Logic Design. Introduction.
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Briefing: Independent NASA Test of RTSX-SU FPGAsComparison of A54SX-A/UMC and RTSX-SU Differences Rich Katz, Grunt Engineer NASA Office of Logic Design
Introduction • The A54SX-A and RTSX-SU series devices are quite similar in many ways. However, there are significant differences in a number of aspects. Those differences will be the subject of this module. • This module applies to UMC produced devices only. • The A54SX-A series of devices are used for • Commercial • Industrial • Automotive • Military high-reliability applications • Spaceflight prototypes. • The RTSX-SU series of devices is designed specifically for spaceflight usage or in other radiation environments.
Family of SX-A, SX-S, and SX-SU FPGAs A54SX32A RTSX32SU RT54SX32S A54SX32A UMC UMC MEC MEC 0.22µm 0.25µm 0.25µm 0.25µm
Architecture and Performance5V CMOS Input Threshold for RTSX-SU VIL VIH Standard Min Max Min Max 3.3V LVTTL and 5V TTL 0.8 2.0 5V CMOS 0.3 Vcci 0.7 Vcci 5.0V PCI -0.5 0.8 2.0 Vcci + 0.5 3.3V PCI -0.5 0.3 Vcci 0.7 Vcci Vcci + 0.5 Source: 5962-01508, Revision C
Architecture and PerformanceIEEE 1149.1 JTAG TRST* Pin • RTSX-SU: • Dedicated pin • Hardwired directly to the TAP controller. • RT54SX-A: • Programmable via an antifuse • Either TRST* or a user I/O function Source: 5962-01508, Revision C
Architecture and PerformanceIEEE 1149.1 JTAG TRST* Pin HARD GROUND THE TRST* PIN Dan says PLEASE ground it. Source: klabs.org - OLD News #7: TRST* and the IEEE JTAG 1149.1 Interface
Architecture and PerformanceCircuit and Process Differences • Performance perspective: each model of device must be analyzed separately • In general, the A54SX-A devices have higher performance and tighter control of delays for parameters such as clock skew. • Power on transient • RTSX-SU: additional components that delays the output buffers coming out of tri-state by approximately 50 ns • No extra delay present in the A54SX-A series devices, resulting in the potential for [extra] glitches as signals propagate through the devices. Source: 5962-01508, Revision C
Architecture and PerformanceClock Delays and Skew A54SX32A RTSX32SU HCLK: tPLH 2.2 4.6 HCLK: tPHL 2.0 4.6 HCLK: tSKEW 0.2 1.9 CLK: tPLH 3.6 5.9 CLK: tPHL 3.8 5.1 CLK: tSKEW 2.2 3.3 Source: Actel data sheets, STD speed grade, VCCI = 3.0V, T = 125 °C Clocks 50% loaded.
Architecture and PerformanceRouting Delays A54SX32A RTSX32SU F0=1 0.6 0.9 FO=2 0.8 1.2 FO=3 1.0 1.6 FO=4 1.3 1.8 FO=8 2.4 3.4 FO=12 3.5 4.7 Source: Actel data sheets, STD speed grade, VCCI = 3.0V, T = 125 °C
Radiation: Total Dose Rev 0. Early version of the RT54SX32S; subsequent devices had a hardened charge pump for tPD sensitivity to total dose.
Radiation: SEU and SET • The R-Cell in the space grade RTSX-SU devices are implemented with the K-Latch that provides redundancy and an asynchronous feedback network such that the flip-flops are effectively made single event upset (SEU) hard without the need for any clock to scrub the triplet. No user-level TMR required. • The clock distribution circuits in the RTSX-SU devices incorporate design features to harden them against single event transients (SETs).
Q D CLK CLK Radiation: SEU Standard master-slave flip-flop, simplified.
AFB D A A' ANQ A A A B A B B B C C C BFB B B' BNQ B A Q CFB C C' CNQ B A G Radiation: SEU K-Latch schematic, simplified. The asynchronous structure and interlocks eliminate the need for a free running clock to scrub SEUs.
Radiation: SEL Current-limit LET = 18 MeV-cm2/mg Some SX-A/UMC models are very latchup susceptible. There are lot-to-lot variations within a particular part number
Antifuse Stress • One measure of antifuse stress, for this class of device, is the ratio of the peak operating current through the antifuse to the programming current through the antifuse. Table 1Normalized IOPERATING/IPROGRAMMING0.25 µm MEC/Tonami process Source: OLD News #16
Antifuse Stress • The RTSX-SU series devices have lower stress levels for the programmed antifuse than their commercial/industrial/military A54SX-A counterparts. Specifically: • One factor which reduces the stress levels is that the RTSX-SU series devices incorporate series resistors at the output of each R-Cell, C-Cell, and I/O Cell which are not present in the A54SX-A series devices. This reduces the peak usage current through the programmed antifuse in the space grade devices. The peak usage current in the A54SX-A is 24% to 55% higher in the A54SX-A series FPGAs when compared to the RTSX-SU devices. • Note that the RTSX-SU devices are built using the 0.25 µm design rules while the A54SX-A devices were scaled down to 0.22 µm. As a result, the RTSX-SU antifuses' programming current is 14% higher then the A54SX-A devices. Additional current during programming will develop a stronger and more robust programmed antifuse for the "low current antifuses." • The above two factors contribute to a lower stress level (ratio of peak operating current to programming current) for the RTSX-SU programmed antifuse when compared with its A54SX-A counterpart, providing additional reliability margin for the space grade device.
