1 / 15

Rich Katz, Grunt Engineer NASA Office of Logic Design

Briefing: Independent NASA Test of RTSX-SU FPGAs Testing and Conditions. Rich Katz, Grunt Engineer NASA Office of Logic Design. Testing and Conditions: Outline. Accelerated Tests Electrical Environment Thermal Environment ATE Testing NASA and Tiger Team Test Comparison

wattan
Download Presentation

Rich Katz, Grunt Engineer NASA Office of Logic Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Briefing: Independent NASA Test of RTSX-SU FPGAsTesting and Conditions Rich Katz, Grunt Engineer NASA Office of Logic Design

  2. Testing and Conditions: Outline • Accelerated Tests • Electrical Environment • Thermal Environment • ATE Testing • NASA and Tiger Team Test Comparison • SEE Testing Discussed Separately

  3. Electrical Environment

  4. DUT Electrical Environment • NASA Header/Driver Card • HCLK = 8 MHz • CLKA = 32 MHz • Supply Voltages • NASA Card: VCC = 5V • VCCI = 4.0V (voltage used to program magnitude of undershoot) • VCCA = 2.75V • I/O Shift Register • Frequency = 8 MHz • Number of SSO’s = 57 (40% of 143) • Pattern and Pattern Length = Ring counter, 5 bits • Average Undershoot = -1V (Room temperature measurement) • Array Shift Register • Frequency = 32 MHz • Pattern and Pattern Length = Ring counter, 2 bits (100% toggling) • Delay Line Frequency = 8 MHz ÷ 8 = 1 MHz

  5. OvershootMAX(mV)

  6. Thermal Environment

  7. DUT Thermal Environment • Test Step Duration: 250 hours per step • Chamber Control Temperatures: • HTOL: +125 C • LTOL: -55 C • Device Power @ 125 C • Power (ICCI): 74mA x 4.00V = 0.295W • Power (ICCA): 350mA x 2.75V = 0.963W • Power (Total): 1.26 watts • Case and Junction Temperatures @ 125 C • Worst-Case Junction Temperature, TCASE = 125 C, no air flow: 153 C • Measured TCASE: 139 C • Absolute Maximum TJ = 150 C

  8. ATE Testing

  9. ATE Test Protocol • Post-Programming Testing • Tri-temperature testing (-55 C, +25 C, +125 C) • 5 minute soak time prior to tests • Intermediate Step Testing • +25 C • Key Point Testing • Tri-temperature testing (-55 C, +25 C, +125 C) • 5 minute soak time prior to tests • Test suite identical, over all temperatures and steps • Results reviewed by two independent teams • Any “out of family” results flagged • Devices either watched or pulled from population for analysis • Criteria can be either an absolute, a relative, or a delta value

  10. Continuity and Shorts cont_setup continuity shorticca shorticci shortiks shortvsv shortvpp Delay Tests delay_test_LH delay_test_HL Functional Tests func_1Mhz_min func_50Mhz_min func_1Mhz_max func_50Mhz_max Leakage Currents, Device standby_icc_oe static_vca static_vci static_vks static_vsv static_vpp Leakage Currents, I/O highz_Max IIL_Inputs_Max_bpmu IIH_BiBuf_Max_bpmu IIL_Inputs_Max_bpmu IIH_BiBuf_Max_bpmu IIL_OE_Max_bpmu IIH_OE_Max_bpmu ATE TestsSorted, Not In Order Performed

  11. Input Thresholds TTL_Vil_Min_Search TTL_Vil50_Min_Search TTL_Vih_Max_Search TTL_Vih50_Max_Search Cmos_Vil_Min_Search Cmos_Vil50_Min_Search Cmos_Vih_Max_Search Cmos_Vih50_Max_Search VOL Testing TTL_Vol1_Min_fun TTL_Vol1_BiBuf_Min_bpmu TTL_Vol1_Outs_Min_bpmu TTL_Vol2_Min_fun TTL_Vol2_BiBuf_Min_bpmu TTL_Vol2_Outs_Min_bpmu Cmos_Vol_Min_fun Cmos_Vol_BiBuf_Min_bpmu Cmos_Vol2_Min_fun Cmos_Vol2_BiBuf VOH Testing TTL_Voh1_Min_fun TTL_Voh1_BiBuf_Min_bpmu TTL_Voh1_Outs_Min_bpmu TTL_Voh2_Min_fun TTL_Voh2_BiBuf_Min_bpmu TTL_Voh2_Outs_Min_bpmu Cmos_Voh_Min_fun Cmos_Voh_BiBuf_Min_bpmu Cmos_Voh2_Min_fun Cmos_Voh2_BiBuf ATE TestsSorted, Not In Order Performed

  12. NASA and Tiger Team Test Comparison

  13. Differences: Tigger Team and NASA Testing (1)

  14. Differences: Tigger Team and NASA Testing (2)

  15. End of rk

More Related